Design of a 7-bit 1 GS/s CMOS Two-Way Interleaved Pipeline ADC
This chapter discusses the design of a 7-bit 1 GS/s time-interleaved pipeline ADC, implemented in a standard digital 0.13 \({\upmu} \) m CMOS technology. All the sub-blocks used in the design of the ADC are also described in this chapter. Furthermore, spe
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Design of a 7-bit 1 GS/s CMOS Two-Way Interleaved Pipeline ADC
Abstract This chapter discusses the design of a 7-bit 1 GS/s time-interleaved pipeline ADC, implemented in a standard digital 0.13 µm CMOS technology. All the sub-blocks used in the design of the ADC are also described in this chapter. Furthermore, specifications for the design and the architecture of the ADC are presented. One of the main objectives of this work was to integrate the proposed current-mode reference shifting (CMRS) MDAC circuit (Sect. 3.2) and verify its functionality in a working ADC structure. As secondary objectives, the proposed amplifier and flash quantizer (Chap. 4) circuits are also to be integrated in this prototype, in order to verify their performance, functionality, and usefulness in a pipeline ADC environment. Notice that, with the integration of both the proposed CMRS-MDAC and flash quantizer, the designed ADC precludes reference voltage circuitry, such as voltage buffers, decoupling capacitors, and damping resistors.
5.1 Specifications The designed ADC prototype was not specified for any particular application. Nevertheless, specifications for the design were given and consisted mainly in proving the functionality of all the proposed circuits described in Chaps. 3 and 4, showing their potential in achieving high energy-efficiency in the design of MDAC-based ADCs. The target specifications for the ADC’s implementation are given in Table 5.1.
5.2 Architecture As mentioned in Table 5.1, a pipeline architecture has been selected to implement the ADC. To relieve the speed requirements of each building block, a two-channel time interleaved architecture is used. Although the time-interleaved structure itself
M. Figueiredo et al., Reference-Free CMOS Pipeline Analog-to-Digital Converters, Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-3467-2_5, © Springer Science+Business Media New York 2013
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5 Design of a 7-bit 1 GS/s CMOS Two-Way Interleaved Pipeline ADC
Table 5.1 Targeted specifications for the designed ADC Parameter
Target
Architecture Structure Technology
Pipeline Fully differential 0.13 µm Single-Poly 8-Metal HS RFCMOS Process 1.2 V 0.5 V (differential) Nyquist 1 Vpp 0.55 V 7-bits 1 GS/s >5 bits ±0.5 LSB ±0.5 LSB
Supply Voltage Reference Signal Bandwidth Input Signal Full-Scale Range Input Signal CM Voltage Resolution Sampling Rate ENOB @ Nyquist INL DNL
Fig. 5.1 Block diagram of the selected architecture for the two-way time-interleaved pipeline ADC
brings other difficulties to the design of the ADC, its benefits outweigh its drawbacks. A simplified block diagram of the overall architecture of the implemented ADC is shown in Fig. 5.1. Concerning the analog part of the system, it is composed of a distributed front-end sample-and-hold (S/H), followed by five 1.5-bit stages and final 2-bit stage. The S/H is distributed to relax its specifications. Although time-interleaved timing mismatch
5.2 Architecture
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Fig. 5.2 Flip-around frontend sample-and-hold circuit
issues would be solved
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