A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends
The growing need for ultra-low power cameras for sensors, surveillance and consumer applications has resulted in significant advances in compressed domain data acquisition from pixel arrays. In this journal we present a novel 64-input Successive Approxima
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Abstract. The growing need for ultra-low power cameras for sensors, surveillance and consumer applications has resulted in significant advances in compressed domain data acquisition from pixel arrays. In this journal we present a novel 64-input Successive Approximation (SAR) Pipeline analog-to-digital converter (ADC) suitable for compressed domain data acquisition in camera front-ends. The proposed architecture features a time interleaved capacitive digital-to-analog converter (DAC) shared between column parallel ADCs for area savings (2.28X); and a shared amplifier stage for power savings (60 %), achieving 4X throughput as compared to traditional architectures. Simulations on a 130 nm foundry process shows that the proposed SAR Pipeline ADC draws 31 µW at 2 MS/s having a target Figure-of-Merit (FOM) of 87 fJ/conv. per step at Nyquist rate. The proposed compressive sensing front end achieves per patch energy per patch of 0.9 nJ.
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Introduction
Mobile devices for IOT (Internet of Things) require CMOS image sensor (CIS) with low power and area [1]. Traditional CIS for wearable devices consume power more than 50 mW [2]. In a CMOS image sensor system the most power consuming blocks are: digital image processing back end & column parallel ADCs [3,4]. In most of the reported image sensors, column parallel ADCs draw 50–65 % of the power of the entire image sensor signal acquisition chip [1,5]. The power consumed by column parallel ADCs is proportional to the number of measurements to be performed by the ADC. It increases with the number of pixels. For next generation IoT devices like “always on” Camera based image sensors, human machine interface systems with built in machine intelligence, low power is the key enabler. Figure 1 shows the traditional nyquist domain signal processing. Pixel voltages are digitized using high speed column parallel ADCs. Digitized image is encoded using algorithms like discrete cosine transform (DCT), discrete wavelet transform (DWT) etc. The power budget for transmitter blocks is shown in c IFIP International Federation for Information Processing 2016 Published by Springer International Publishing AG 2016. All Rights Reserved Y. Shin et al. (Eds.): VLSI-SoC 2015, IFIP AICT 483, pp. 131–149, 2016. DOI: 10.1007/978-3-319-46097-0 7
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Fig. 1. Traditional nyquist signal acquisition and transmission
Fig. 2. Power budget for various blocks in transmitter
Fig. 2. We can observe that encoding part like DCT, DWT consumes significant amount of power followed by Analog to Digital signal acquisition etc. As the resolution of the image goes up the number of measurements per ADC goes up and hence the encoding power also increases. This places huge power constraint on acquisition device and transmitter. Recently developed algorithms of compressive sensing (CS) promise to reduce the number of measurements with non-linear recovery at the back-end [6]. The signal processing chain for compressing sensing is shown in Fig. 3. This approach makes the encoding done at the transmitter si
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