Design of DA-Based FIR Filter Architectures Using LUT Reduction Techniques
The multiplier-less techniques such as distributed arithmetic (DA) have gained large popularity for its high-speed processing. Architectures based on DA results in cost-efficient and area-efficient structures. This paper presents design and realization of
- PDF / 286,435 Bytes
- 10 Pages / 439.37 x 666.142 pts Page_size
- 70 Downloads / 180 Views
Abstract The multiplier-less techniques such as distributed arithmetic (DA) have gained large popularity for its high-speed processing. Architectures based on DA results in cost-efficient and area-efficient structures. This paper presents design and realization of various DA-based FIR filter architectures based on LUT reduction techniques of length N = 4 and also implemented using both shift accumulators and carry save shift accumulators. The larger LUT is subdivided into a number of LUTs to reduce the size of the LUT for higher order filter. FIR filter architectures designed include filter with LUT size of 2N − 1 words, filter with LUT size of 2N − 1 words, filter with LUT breakup contains two 2N/2 − 1 word LUTs, and also LUT-less filter but only has combinational blocks. These filter architectures have been synthesized for the target FPGA device and results are compared based on RTL area, device utilization, maximum operating frequency, and power consumption. Keywords Distributed arithmetic (DA) Shift accumulation (SA)
Carry save shift accumulator (CSSA)
1 Introduction Multiply and accumulate operation is very common in all digital signal processing algorithms such as finite impulse response (FIR) filter. As multipliers consume more area and power in multiply and accumulate (MAC) operation of FIR Filter, several multipliers-less schemes have emerged. Distributed arithmetic (DA) method is one of the multiplier-less techniques which uses memories (RAMs, ROMs) or LUTs to store precomputed values of coefficient operations [1]. DA is an efficient technique for performing multiply-and-add in which the multiplication is reorganized such that multiplication and addition are performed on data and single bits of the coefficients, at the same time [2]. The inner products containing many terms can A. Uma (&) P. Kalpana T. Naveen Kumar Department of ECE, PSG College of Technology, Coimbatore, India e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2018 V. Nath (ed.), Proceedings of the International Conference on Microelectronics, Computing & Communication Systems, Lecture Notes in Electrical Engineering 453, https://doi.org/10.1007/978-981-10-5565-2_20
221
222
A. Uma et al.
be partitioned into a number of smaller inner products which can be computed and summed by using either DA or an adder. Hence, DA is widely used for the implementation of digital filters [3]. The advantages of DA are best exploited in data-path circuit designing. DA efficiently implements the MAC using basic building blocks (Look-up Tables) in FPGAs. These DA structures can be used even in adaptive filters. An adaptive filter which is commonly used in devices such as mobile phones, camcorders. This adaptive structure is a system with a linear filter that has a transfer function controlled by variable parameters and a means to adjust those parameters according to an optimization algorithm [4]. Adaptive filters are required for some applications because some parameters of the desired processing operation are not known in advance or are changing [5].
Data Loading...
