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B9.18.1

Dopant Activation in bulk germanium and Germanium-on-Insulator Y.-L. Chao, S. Prussin, J. C. S. Woo University of California, Los Angeles, Department of Electrical Engineering, USA R. Scholz Max-Planck Institute of Microstructure Physics, Halle/Saale, Germany Abstract High levels of electrical activation of both p- and n-type dopants are realized by pre-amorphization implantation (PAI) in bulk germanium wafers and germanium-oninsulator (GOI) substrates. In bulk germanium, p-type dopant yields an electrical activated concentration of 1.5×1020 /cm3 after a 400°C rapid thermal annealing (RTA), which is one order higher than obtained for samples without PAI. N-type dopants also show comparable improvement as 1×1020 /cm3 after 600°C RTA. Both results are the highest ever being reported and are sufficient for advanced CMOS applications. PAI was also employed in dopant activation for GOI substrates. Carrier concentrations of 6×1020 /cm3 and 5×1019 /cm3 were observed for p- and n-type dopants respectively after identical RTA conditions as for bulk germanium counterparts. Hydrogen incorporated in GOI wafers which were prepared by Smart-CutTM approach may be responsible for the discrepancy of activated concentrations between bulk germanium and GOI. Nevertheless, PAI shows the promise of dopant activation in germanium and can be readily adopted in current CMOS processes. Introduction As silicon based metal-oxide-semiconductor field effect transistor (MOSFET) devices continue to be scaled down, a number of challenges arise. Gate leakage current and carrier transport limited by reduced mobility, velocity saturation and source/drain parasitic resistance are two of the major obstacles. Replacement of silicon oxide with a high-K dielectric film offers a possible reduction of gate leakage current; however, with a penalty of mobilities degradation due to phonon scattering. [1] Carrier transport limitation may be mitigated by the incorporation of a more efficient carrier injection material. Thus, new channel materials such as strained silicon or pure germanium [2] appear to be viable options for sub-100nm transistors. Germanium regains attention for its superior electron and hole low field mobilities. Its small bandgap may also reduce the source/drain parasitic resistance, provided the possible smaller Schottky barrier height. On the other hand, the implementation of germanium MISFETs in a volume production line is hindered by its cost, weight, and mechanical strength. Germanium-on-Insulator (GeOI) with a silicon host wafer, therefore, is a platform of choice for industry. Dopant activation has been one of the major obstacles in fulfillment of Ge MISFETs, especially for n-MISFETs. The difficulty arises from the low solid solubility of n-type and p-type dopants and the high diffusion coefficient of n-type dopants in germanium. Studies on activation using furnace annealing [3] [4] and rapid thermal annealing (RTA) [5] have been widely reported by several groups. The best achievable

B9.18.2

results employed RTA at temperature