Physical Modeling of Defects, Dopant Activation and Diffusion in Aggressively Scaled Bulk and SOI Devices: Atomistic and
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0912-C05-05
Physical Modeling of Defects, Dopant Activation and Diffusion in Aggressively Scaled Bulk and SOI Devices: Atomistic and Continuum Approaches Victor Moroz, and Ignacio Martin-Bragado Synopsys, 700 East Middlefield Road, Mountain View, CA, 94043
ABSTRACT In this overview we examine how advanced continuum and atomistic modeling can help to understand and resolve process and device design issues for the 65 nm technology generation and beyond. The following implantation-related issues are reviewed: wafer temperature for different types of implant equipment and its impact on defect formation and amorphization, ion scattering off the photoresist mask and its impact on threshold voltage variation, dual rotation halo implant instead of the conventional quad rotation halo implant, and engineering of the source/drain junction overlap for diffusionless annealing by using tilted implants. The following annealing-related issues are also considered: limitations of spike anneal; benefits of cocktail junctions, heat transfer mechanisms for spike and millisecond annealing, and implant damage evolution for different thermal budgets. Taken together, implant, annealing, and layout conditions are shown to explain observed threshold voltage and transistor performance variations. In addition, the effects of transistor geometry on dopant diffusion, activation, and defect formation are shown for several generations of bulk and FDSOI MOSFETs. INTRODUCTION Scaling down the thermal budget for junction annealing and shrinking the vertical and lateral dimensions of a transistor often bring process integration issues or unexpected effects that either shift device performance into an undesirable range or introduce increased layout sensitivity. In this paper, we use continuum and atomistic process simulation tools to explore some of these issues that are expected to influence device technology within the next decade. IMPLANTATION Going from batch to single wafer The semiconductor industry is undergoing a transition from batch implanters to single wafer implanters. These two types of the implant tools have very distinct patterns of ion beam scanning. The conventional batch tools scan several hundred times over each patch of the silicon wafer, with each scan spending about 1 ms over a point on the surface of the wafer. The new single wafer implant tools typically have ten times fewer ion beam scans (i.e. several tens), with each scan having one tenth of the current density and hundred times longer duration (i.e. about 100 ms over a point on the wafer surface). This difference in the scanning patterns leads to distinct wafer temperature evolution during the implant. Figure 1 compares temperature evolution at the surface of a silicon wafer for the two implanters.
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Wafer tempeature (C)
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Single-wafer
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Implantation time (s) Figure 1. Temperature evolution of the wafer surface for the batch and the single wafer implanters. The overall amount of energy deposited by the ions is the same f
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