Double-Ion-Implanted GaN MESFETs with Extremely Low Source/Drain Resistance
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0892-FF13-06.1
DOUBLE-ION-IMPLANTED GaN MESFETs WITH EXTREMELY LOW SOURCE/DRAIN RESISTANCE Kazuki NOMOTO*, Nobuyuki ITO*, Taku TAJIMA*, Takeshi KASAI**, Tomoyoshi MISHIMA***, Taroh INADA*, Masataka SATOH*, Tohru NAKAMURA* *Department of EECE and Research Center of Ion Beam Technology, Hosei University Koganei, Tokyo 184-8584 Japan **Chemitronics, Musashimurayama, Tokyo208-0023, ***Hitachi Cable, Tsuchiura, Ibaraki 300-0026 Tel:+81-42-387-5104, E-mail:[email protected] ABSTRACT Incorporation of Si ion implantation to GaN metal semiconductor field effect transistor (MESFET) processing has been demonstrated. The channel and source/drain regions formed using Si ion implantation into undoped GaN on sapphire substrate. In comparison with the conventional devices without ion implanted source/drain structures, the ion implanted devices showed excellent device performance. On-state resistance reduces from 210 ohm-mm to 105 ohm-mm. Saturation drain current and maximum transconductance increase from 36 mA/mm to 78 mA/mm and from 3.8 mS/mm to 10 mS/mm, respectively. INTRODUCTION GaN FETs are expected as high breakdown and high speed devices, because GaN is a wide bandgap semiconductor material, with a high breakdown electric field, high saturation drift velocity, and good thermal conductivity as compared to GaAs and SiC. Therefore, GaN devices have a possibility for expanding application of the high frequency and power devices (1-3). In order to make these devices highly efficient, reduction of on-state resistance is important. There are many reports on fabricating high concentration layers below source/drain contacts to reduce the on-state resistance. Ion implantation is one of the most indispensable technologies for impurity doping to fabricate high concentration regions especially in silicon based integrated circuits. However, a few reports are published on application of ion implantation to the active regions except for isolation in GaN devices, because the complicated technologies such as hot ion implantation are needed to prevent damage induced by ion implantation. The activation and crystal damage recovery of implanted GaN also require annealing at temperatures above 1500 oC. In this paper, we demonstrate the incorporation of Si ion implantation to GaN metal semiconductor field effect transistor (MESFET) processing. Source and drain with heavily doped regions were made to use ion implantation technology. Silicon ions were implanted into channel and source/drain regions on GaN on a sapphire substrate at room temperature, and high activation rates were achieved at temperature below 1200 oC. In comparison with the conventional devices without ion implanted source/drain structures, the ion implanted devices showed excellent device performance.
DEVICE STRUCTURE A 2 um thick undoped GaN layer was grown by metal-organic vapor phase epitaxy
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Source Ti/Al(50/200nm)
Gate Ni/Al(50/100nm)
Drain Ti/Al(50/200nm)
SiNx
n+
I/I Channel Region
Heavily Ion Implanted Region Si+ : 80 keV, 1×1015/cm2
n+ GaN UID 2
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