Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware
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Dynamic power‑aware scheduling of real‑time tasks for FPGA‑based cyber physical systems against power draining hardware trojan attacks Krishnendu Guha1 · Atanu Majumder1 · Debasri Saha1 · Amlan Chakrabarti1
© Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks. Keywords Hardware trojan horse · Real-time task scheduling · Power draining attack · FPGA
* Krishnendu Guha [email protected] Extended author information available on the last page of the article
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Abbreviations FPGA Field-programmable gate array IP Intellectual property 3PIP Third party IP vendor HTH Hardware trojan horse HDL Hardware description language DPR Dynamic partial reconfiguration DCM Dynamic clock management PTI Periodic task interface NPTI Non-periodic task interface CU Control unit TIA Task information analyzer EDF Earliest deadline first TSR Task success rate TRR Task rejection rate NPB Normalized power budget NToA Normalized time of attack NTRD Normalized task relative deadline VLSI Very large scale integration List of symbols fn Total number of FPGAs vn Total number of 3PIP vendors v Variable which indexes the number of vendors b Total
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