EBIC Analysis of Geitering at Si-Si(Ge) Heteroepitaxial Misfit Dislocations as a Function of Impurity Decoration
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EBIC ANALYSIS OF GEITERING AT Si-Si(Ge) HETEROEPITAXIAL MISFIT DISLOCATIONS AS A FUNCTION OF IMPURITY DECORATION H.R. KIRK, Z.J. RADZIMSKI, E.A. FITZGERALD*, AND G.A. ROZGONYI Dept. of Materials Science and Engineering, North Carolina State University, Raleigh North Carolina, 27695
*AT&T Laboratories, Murray Hill, New Jersey ABSTRACT An EBIC analysis is made of decorated heteroepitaxial misfit dislocations formed at the interface of Si-Si(Ge) epitaxial layers grown in a CVD reactor on Si substrates. The electrical activity of the dislocations is studied after decorating the dislocations with Ni and Au impurities introduced by ion-implantation and backside deposited metallic thin films. The impurities are activated by RTA annealing at 400, 800 and 1000*C. A model is
presented for the formation of NiSi 2 precipitates on misfit dislocations which suggests that the nucleation and growth of NiSi 2 precipitates is a function of the cleanliness of the
as-grown dislocations. It is concluded that the distribution of electrical activity of impurity decorated misfit dislocations is a strong function of the impurity type, condition of the as-grown material, and concentration of metallic impurities introduced during the process of decoration. INTRODUCTION A number of applications have been proposed for heteroepitaxial misfit dislocations that form at the boundaries of Si and Si(Ge) epitaxial layers. Extrinsic gettering [11 is one of these applications and the most simple to employ because gettering is primarily a chemical property. The dislocations are located a safe distance from electronic devices, and the electrical activity of the dislocations is not particularly important. Other proposed applications [2,3] such as, microwires, enhanced recombination centers and voltage controlled dislocations rely on the electronic properties of misfit dislocations. If these applications are to be successful then it is important to develop a fundamental understanding of processing techniques that produce dislocations with a uniform spatial distribution of electrical properties over the entire length of individual dislocations. In this work an experiment was conducted to test the spatial distribution of electrical activity along dislocations that have been decorated with the impurities Ni and Au. The electrical activity is evaluated using a scanning electron microscope, SEM, operated in the electron beam induced current mode, EBIC, on Si(Ge)/Si samples before and after decoration. EXPERIMENTAL A cross grid of epitaxial misfit dislocations was formed by growing a buried 2% Ge Si(Ge) alloy layer on four inch diameter Si substrates between pure Si capping and buffer layers. The epitaxial layers were grown at 1120"C in a CVD reactor. The layers were n-type nominally doped to 5x10 14 cm- 2 on n-substrates. The capping, alloy and buffer layers were 2.7, 1.4 and 2 gIm thick respectively. The thickness of the capping and Mat. Res. Soc. Symp. Proc. Vol. 262. 01992 Materials Research Society
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alloy layers were measured by Nomarski microscopy
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