Effect of Metal - Silicon Nanowire Contacts on the Performance of Accumulation Metal Oxide Semiconductor Field Effect Tr
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1144-LL06-02
Effect of Metal - Silicon Nanowire Contacts on the Performance of Accumulation Metal Oxide Semiconductor Field Effect Transistor. Pranav Garg1,Yi Hong1, Md Mash-Hud Iqbal2, and Stephen J. Fonash1 1. Center for Nanotechnology Education and Utilization, The Pennsylvania State University, University Park, PA, USA. 2. Centre for Advanced Photonics and Electronics, University of Cambridge, Cambridge, United Kingdom. ABSTRACT Recently, we have experimentally demonstrated a very simply structured unipolar accumulationtype metal oxide semiconductor field effect transistor (AMOSFET) using grow-in-place silicon nanowires. The AMOSFET consists of a single doping type nanowire, metal source and drain contacts which are separated by a partially gated region. Despite its simple configuration, it is capable of high performance thereby offering the potential of a low manufacturing-cost transistor. Since the quality of the metal/semiconductor ohmic source and drain contacts impacts AMOSFET performance, we repot here on initial exploration of contact variations and of the impact of thermal process history. With process optimization, current on/off ratios of 106 and subthreshold swings of 70 mV/dec have been achieved with these simple devices.
INTRODUCTION Field effect transistors (FET) based on semiconductor nanowires (NW) have received enormous attention due to their potential applications as building blocks for future nanoscale electronics [14]. Many of these NW FET devices are fabricated on single doping type NW with metallic source/drain (S/D) Schottky barriers (SB) contacts and a back gate. Many function as accumulation channel devices but show strong ambipolar conduction [2, 3], large hysteresis [4], and current-voltage (I-V) characteristics that are limited by S/D Schottky barrier contacts [3, 4]. Efforts to suppress ambipolar behavior and improve I-V characteristics such as double gate structures [3] and/or S/D contact doping [4] require additional processing steps and face the challenges of channel length scaling. The AMOSFET offers a very simple device configuration that can give high performance unipolar transistors (on nanowires, nanoribbons or thin films) while avoiding complex processing steps. Figures 1a and 1b schematically show the AMOSFET configurations on a semiconductor thin film and on a nanowire, respectively. As shown, the AMOSFET configuration only requires a single doping type semiconductor as the active layer, ohmic source and drain contacts spaced at minimum required distance from the gate, a minimum length gate, and a nano-scale dimension perpendicular to the gate [5-8]. Extensive numerical simulations of the AMOSFET configuration have shown that the nanoscale dimension perpendicular to the gate required in AMOSFETs makes it possible for the gate to control on-state current conduction via accumulated majority carriers and off-state behavior through depletion of majority carriers [5,6]. The gate dielectric thickness and dielectric constant are not critical since the AMOSFET I-V characteristic
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