Effect of Nickel Silicide Induced Dopant Segregation on Vertical Silicon Nanowire Diode Performance
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Effect of Nickel Silicide Induced Dopant Segregation on Vertical Silicon Nanowire Diode Performance W. Lu1,3,4, K. L. Pey1,2, N. Singh3, K. C. Leong4, Q. Liu5, C. L. Gan5, G. Q. Lo3 , D. -L. Kwong3 and C. S. Tan1 1
School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore. Singapore University of Technology & Design (SUTD), Singapore. 3 Institute of Microelecrtonics, A*STAR (Agency of Technology & Research), Singapore. 4 GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore. 5 School of Materials Science and Engineering, Nanyang Technological University, Singapore. 2
ABSTRACT In this work, Dopant Segregated Schottky Barrier (DSSB) and Schottky Barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated on p-type Si substrate using CMOScompatible processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing processes on nickel silicide formation in DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher oncurrent, due to an enhanced carrier tunneling, and much lower leakage current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also gave ideality factor much closer to unity and exhibited lower electron SBH (ĭBn) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by ~ 5X and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to 1-step DSSB VSiNW diode. INTRODUCTION Silicon nanowires (SiNWs) [1-3] are viewed as serious contender for technology nodes beyond 14 nm because SiNWs can provide gate-all-around (GAA) transistor architecture to boost the gate electrostatic control over the channel inversion. In order to take full advantage of the GAA nanowire geometry, vertical nanowires (VSiNWs) are preferred. This is because they occupy smaller estate area than planar transistors at the same technology node, and they resolve the problems, such as gate definition under the wire and gate etching on the wire, faced by lateral nanowires [4]. Contact and series resistances of source/drain regions pose a serious problem for SiNW transistors. In order to alleviate this issue, Schottky Barrier (SB) junctions, formed via rapid thermal annealing (RTA) and/or laser annealing [5-9], are introduced. With its metal-like
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resistance, SB junctions offer an alternative to doped S/D regions. However, SB junctions are associated with Schottky Barrier Height (SBH) which impedes the charge carrier flow and affects th
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