Effect of Submicron Structural Parameters on the Performance of a Multi-Diode CMOS Compatible Silicon Avalanche Photodet
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HYSICS OF SEMICONDUCTOR DEVICES
Effect of Submicron Structural Parameters on the Performance of a Multi-Diode CMOS Compatible Silicon Avalanche Photodetector K. Majumdera,*, P. Rakshitb, and N. Ranjan Dasb a Academy
of Technology, Maulana Abul Kalam Azad University of Technology, G. T. Road, Adisaptagram, Aedconagar, Hooghly, WB, 712121 India b Institute of Radio Physics and Electronics, University of Calcutta, 92, A. P. C. Road, Kolkata, WB, 700009 India *e-mail: [email protected] Received February 2, 2020; revised May 14, 2020; accepted May 15, 2020
Abstract—We present a theoretical study on gain and bandwidth of a CMOS-compatible submicron multidiode Si avalanche photo-detector suitable for operation at high speed and moderate voltage. A two-dimensional model is used to obtain the avalanche build-up of carriers in the depleted region considering the deadspace effect. The regions between fingers are discretized to sub-regions, and the carriers are specified by their energy and position indices. The model also considers the effects of carriers diffusion from the substrate region, and the parasitic effects due to the presence of multiple diodes in lateral configuration. The gain and frequency response data obtained from the model are shown to be in good agreement with experimental data taken from literature. The results are shown for variation of gain and bandwidth with substrate thickness, finger spacing, and number of diodes. It has also been shown that there exists optimum choice of substrate thickness so that the gain–bandwidth product reaches maximum keeping other parameters constant. Keywords: dead-space effect, impact ionization, lateral CMOS p–i–n, Si-avalanche photo-detector, gain– bandwidth DOI: 10.1134/S1063782620090183
1. INTRODUCTION Optical receiver is an important building block in any optical communication system. III–V materials are suitable for their high performance in such applications, but the technology is relatively expensive compared to silicon CMOS technology. Though silicon has the drawback of low efficiency for optoelectronic devices due to its indirect band gap, its advantages are manifold to use for commercial applications, particularly for local area networks, chip-to-chip and board-to-board optical interconnections in optical access networks, and high-speed data links [1–4]. Fully integrated optical receivers with integrated silicon photodiodes provide additional advantages of silicon-based photo-detectors (PD). Thus, silicon CMOS optoelectronic integrated circuits (OEICs) have been a target of active research efforts in recent years [5–10]. Though Si-based detectors grown in vertical configuration have been reported to have improved performance, the lateral configuration is more favored from the viewpoint of integration of the photo-detectors with MOSFETs using CMOS technology. In lateral configuration, responsivity can be increased by using a thick substrate, but the contribution of photo-generated carriers from the heavily
doped substrate region to the photocurrent b
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