Effect of Spacer Scaling on PMOS Transistors
- PDF / 63,343 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 81 Downloads / 227 Views
0913-D03-04
Effect of Spacer Scaling on PMOS Transistors Wai Shing Lau1, Chee Wee Eng2, David Vigar2, Lap Chan2, and Soh Yun Siah2 1 School of EEE, Nanyang Technological University, NTU, School of EEE, Block S2.1, Nanyang Avenue, Singapore, Singapore, 639798, Singapore 2 Chartered Semiconductor Manufacturing Ltd, Woodlands Industrial Park D St. 2, Singapore, Singapore, 738406, Singapore
ABSTRACT Our observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.
INTRODUCTION As CMOS technology is scaled down to smaller dimensions, the effective channel length (Leff) of MOS transistors becomes smaller and smaller. The spacer also becomes smaller in size and gradually conventional spacer process migrates to L-shaped spacer process. During state-ofthe-art CMOS integrated circuit manufacturing, we observed that the p-channel MOS (PMOS) transistor shows up a sizeable increase in the on-current and off-current when the L-shaped spacer becomes slightly smaller. The effect of a slightly smaller spacer is pretty weak for the corresponding n-channel MOS (NMOS) transistor. It is known that boron TED (transient enhanced diffusion) and BED (boron enhanced diffusion) of the p-type source/drain extension induced by the p-type deep source/drain implant have strong effects on PMOS transistors [1]. Si interstitials generated by implant damage (TED) or the presence of a large quantity of B (BED) can enhance B diffusion through the following reaction: BS + I ↔ BI ,
(1)
where BS is the substitutional boron, I the Si self-interstitial and BI the interstitial-assisted mobile boron. 0.11 µm CMOS technology using L-shaped spacer technology was used to fabricate MOS transistors. For our experiment, liner spacer splits A and B have a liner spacer thickness of 8 and 12 nm, respectively. We can easily imagine that there are two possible physical mechanisms which can increase the on-current. Mechanism A is that the effective channel length becomes smaller. It can be imagined that a slightly smaller spacer reduces the distance between
the p-type deep source/drain implant and the channel region, resulting in stronger boron TED (transient enhanced diffusion) and BED (boron enhanced diffusion) of the p-type source/drain extension, which can cause a reduction if the effective channel length (Leff) of the PMOS transistor. This will cause a significant increase in the on-current and off-current. Mechanism B is that the drain/source series resistance becomes smaller. It can also be imagined that a slightly smaller spacer can cause a reduction in
Data Loading...
