Toward Ultimate Scaling: From FinFETs to Nanosheet Transistors
In this work, a TCAD-based simulation approach has been proposed to analyze 3-nm long p-type nanosheet (NS) field-effect transistors (FETs). The effects of the number of conducting channels on device performance have been studied in detail. As a proof-of-
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Abstract In this work, a TCAD-based simulation approach has been proposed to analyze 3-nm long p-type nanosheet (NS) field-effect transistors (FETs). The effects of the number of conducting channels on device performance have been studied in detail. As a proof-of-concept, the advanced nonplanar FinFET, nanowire FET, and nanosheet FET are compared. Nanosheet transistors show the best performance, and it seems to be the most suitable contender for future technology nodes. Keywords Nanosheet FETs · FinFETs · Nanowire · 3 nm · Linearized Boltzmann transport (LBT) · TCAD
1 Introduction The microelectronics industry is facing increasing physical dimensional limits; the gate length in particular cannot be reduced due to its fundamental limit and also the precision of the manufacturing processes (mainly the lithography). Transistors today are in the nanometer range. The TSMC has even opted for this solution for T. P. Dash (B) · E. Mohapatra · C. K. Maiti Department of Electronics and Communication Engineering, ITER, Siksha O Anusandhan (Deemed to be University), Bhubaneswar 751030, Odisha, India e-mail: [email protected] E. Mohapatra e-mail: [email protected] C. K. Maiti e-mail: [email protected] S. Das Department of Electronics and Communication Engineering, Silicon Institute of Technology, Bhubaneswar 751024, India e-mail: [email protected] S. Choudhury Department of Electrical and Electronics Engineering, ITER, Siksha O Anusandhan (Deemed to be University), Bhubaneswar 751030, India e-mail: [email protected] © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 R. Sharma et al. (eds.), Green Technology for Smart City and Society, Lecture Notes in Networks and Systems 151, https://doi.org/10.1007/978-981-15-8218-9_19
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its 16 nm technology node, whereas Samsung and GlobalFoundries 14 nm node are now in production. Intel has implemented circuits with transistors at 10 nm technology node, and GlobalFoundries is actively working on making transistors at 7 nm technology node. It was a fin-shaped trigate nonplanar MOSFET (also called trigate FinFET), which shows superior subthreshold performance due to better gate control. In this architecture, the current flows in long vertical flanks that is why it is better to make narrow FinFETs (for better control of the electrostatics). The 3-D geometry of such nonplanar FinFET structures imposes new challenges, especially at the computational level. Thus, it becomes essential to choose the appropriate transport model for nanoscale nonplanar devices in advance technology nodes. The physical behavior of carriers inside nonplanar FinFETs is not as simple as in planner devices. A minimal number of research reports are available till date explaining carrier transport phenomena at nanoscale. Accurate simulation of these nonplanar devices and their modeling aspects have several challenges to overcome. At nanoscale, the incorporation of quantum effects in the transport model i
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