Scaling Transistors into the Deep-Submicron Regime
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into the DeepSubmicron Regime Paul A. Packan
Introduction The dominant device used in the semiconductor industry today is the siliconbased metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). The source region provides a supply of mobile charge when the device is turned “on.” The source is electrically isolated from the drain by the channel region, which is oppositely charged. An insulating oxide layer between the gate and the channel region forms a capacitor. During operation, a voltage is applied to the gate. By applying the appropriate voltage, a conductive layer of charge can be attracted in the
channel region at the oxide/silicon interface. This layer of charge acts as a wire that effectively connects the source and drain regions. By changing the voltage on the gate, the conducting layer of charge can be removed. Thus the transistor acts like a switch, with the gate electrode controlling the connection from the source to the drain. These individual switches can be connected to form the basic building blocks for circuit design. These building blocks are used to create the high-performance microprocessors and memory chips in today’s computers. Improvements in the computer industry over the past 30 years have relied heavily
Figure 1. Cross-section micrograph of a metal oxide semiconductor (MOS) transistor.
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on the ability to increase the speed of the silicon transistor. This increase in speed has come largely through the downward scaling of the dimensions of the device. Device scaling requires that all vertical and lateral dimensions of the transistor be scaled (see device features in Figure 1).1 However, scaling the depth and width of the source and drain regions decreases the amount of free charge and can result in an unacceptable increase in device resistance. In order to maintain a low device resistance as the device is scaled down, the charge concentration in the source and drain regions must be increased. To maintain good electrical isolation between the source and drain regions, the concentration of charge in the channel region must also increase. Therefore, in order to scale down the MOS transistor, the concentration of charge in the source, drain, and channel regions must increase while the vertical and lateral dimensions are decreased. This combination of increased concentration and improved confinement has been a major focus of device development for the past 10 years (see Figure 2).
Device Engineering The charge in the source, drain, and channel regions of the MOS transistor is formed by locally adding dopant atoms to the silicon lattice. Silicon is a covalently bonded material with four nearest neighbors. Adding to the silicon lattice a dopant atom that has five valence electrons results in a negative charge that is not locally bound but is free to move in the lattice. This type of doped silicon material is widely referred to as n-type silicon. Likewise, adding a dopant atom that h
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