Effects of High Temperature Process Steps on Void Size Distributions in Passivated, Narrow Aluminum Lines
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EFFECTS OF HIGH TEMPERATURE PROCESS STEPS ON VOID SIZE DISTRIBUTIONS IN PASSIVATED, NARROW ALUMINUM LINES D. A. Lilienfeld* and P. Borgesen** *National Nanofabrication Facility, Cornell University, Ithaca, NY 14853 "**Department of Materials Science and Engineering, Cornell University, Ithaca, NY 14853 ABSTRACT Narrow Al lines were passivated at 300'C and subsequently annealed at 400'C for an hour. The passivation layer was then removed and the lines analyzed for thermal stress induced voids. Effects of the multiple high temperature process steps necessary in chip manufacturing were simulated by repeated anneals. Renewed void nucleation occurred during cool-down from each anneal, leading to a systematic increase in void density. In contrast, the maximum void size did not increase with number of anneals while it did increase with aging time for a single anneal. INTRODUCTION One of the first cavity-driven failure modes observed in narrow lines was electromigration. This failure mode has been studied extensively since the 1960's and many aspects of the behavior are well documented. In the 1980's, a new cavity failure mode was observed: Thermal stress induced voiding[1, 2, 3] in passivated narrow lines. In this mechanism mass transport occurs in lines which are not carrying current, so line failures can occur while the device is sitting on the shelf or the device is turned off. These voids have been linked to residual stresses in the lines due to the presence of the passivation layer[4, 3, 5] which serves at least three purposes: 1) Electrical insulation. 2)Protection of the lines from corrosion and 3) Reduction of the rate of electromigration failure. Two types of thermal stress induced voids are observed: slit like voids and irregularly shaped voids[61 . The slit-like voids often cross the whole narrow line and cause opens. A clear line width dependence on the thermal stress voiding has been observed with the mean time to failure being a strong inverse function of the linewidth. Recent theoretical work has offered an explanation of the driving force for the mass transport during thermal stress voiding[7, 8] and provides a sound basis for the modeling of lifetimes due to thermal stress voiding. Besides an obvious concern about stress induced failure, thermal stress induced voids are also important because of an expected correlation with electromigration[9,101. Recent work has argued that the thermal stress induced voids can serve as nucleation sites for electromigration failure and that much electromigration induced voiding can be explained by the current driven coalesence of thermal stress voids[11l. A model which includes grain boundary trapping of the current driven voids can explain the electromigration lifetimes, current dependences and many other aspects of electromigration[121 Based on measurements of void growth and stress relaxation, substantial progress has been made towards an understanding of the development of 'typical' thermal stress voids with time. Voids are known to nucleate and start to grow Mat. Res
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