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Effects of Post-Deposition Annealing Temperature on Band Alignment and Electrical Characteristics of Lanthanum Cerium Oxide on 4H-SiC Way F. Lim1 and Kuan Y. Cheong1 1 Energy Efficient & Sustainable Semiconductor Research Group, School of Materials & Mineral Resources Engineering, Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia ABSTRACT Investigation of lanthanum cerium oxide as a gate oxide on 4H-SiC was performed by varying post-deposition annealing temperature from 400 to 1000°C. Energy band alignment and band gap of bulk oxide and interfacial layer (IL) with respect to SiC were extracted using X-ray photoelectron microscopy. Two band alignment structures were proposed and the change of band alignment was affected by the changes in chemical composition in bulk oxide and in IL that may induce lattice strains and dipoles. A conduction band offset of IL/SiC was 0.97 eV for sample annealed at 1000°C, which was comparable to the value extracted from Fowler-Nordheim model. The acquisition of sufficient conduction band offset, coupled with the lowest slow trap density, effective oxide charges, interface trap density, as well as total interface trap density, yielded the lowest leakage current density for this sample. INTRODUCTION A vast of research efforts have been contributed to investigating high dielectric constant (k) oxides for silicon carbide (SiC)-based metal-oxide-semiconductor (MOS) devices due to the limitation imposed by the traditional SiO2. Although a high k is a necessary requirement for SiCbased MOS devices, maximizing k does not necessarily lead to an optimum performance [1]. One of the challenges in implementing high k oxides into SiC-based MOS devices is the low band offset at the high k oxide/SiC interface. This drawback can be overcome by introducing an interfacial layer of SiO2 or silicate between the high k oxide and SiC substrate [1]. Nevertheless, the formation of interfacial layer tends to change the band alignment of the device, leading to asymmetric band offsets. This could be attributed to the presence of dipoles at the interface that will affect both the conduction and valence band offset [2]. As a consequence, higher leakage current is unavoidable and the device operation will be affected due to an adverse effect of band offset variation on effective flatband voltage [2]. In this work, lanthanum cerium oxide (LaxCeyOz), which has been recently utilized as a potential high k oxide on Si substrate [3], is investigated on 4H-SiC by varying the post-deposition annealing temperature from 400 to 1000°C. Similar work has been carried out to examine the physical characteristics of the film [4]. However, electrical performance of the film has not been explored. Therefore, it is of great interest to investigate for the first time the possible band alignment of lanthanum cerium oxide on 4H-SiC using X-ray photoelectron microscopy (XPS) and its electrical characteristics in order to explore its potential for SiC-based MOS devices. EXPERIMENTAL