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EFFECTS OF TEMPERATURE AND ELECTRICAL STRESS ON THE CHARACTERISTICS OF AMORPHOUS SILICON THIN-FILM TRANSISTORS

JIN S. PARK, CHANG H. OHS, HONG S. CHOI5 , MIN K. HAN, YEARN I. CHOI==, AND CHUL H. HAN*** Seoul Nat'l. Univ., Dept. of Electrical Eng., Kwanak-Ku, Seoul 151-742, Korea 5 GoldStar Co., LTD., R & D Complex, An-Yang 430-080, Korea 5 *Ajou Univ., Dept. of Electronics Eng., Suwon 440-749, Korea 5 **KAIST, Dept. of Electrical Eng., Daejeon 304-350, KOREA

ABSTRACT The experimental and analytical results regarding to the effects of temperature and electrical stress on the characteristics of amorphous silicon thin-film transistors (a-Si TFT's) have been presented. The variations in the device parameters of a-Si TFT, such as threshold voltage and field-effect mobility, have been examined under various operating temperatures and electrical stress conditions. The hysteresis in the transfer characteristics and the trapped charges at the a-Si/silicon nitride interface were measured at the operating temperature ranges. From the experimental results, it has been found out that the increase of the interface charge trapping may be responsible for the degradation in the a-Si TFT characteristics. Also, an analytical formulation, employing the interface charge trapping, is presented to clarify the instability phenomena and verified successfully with the experimental results. INTRODUCTION Amorphous silicon~a-Si) thin-film transistors(TFT's) have been emerged as a prime switching-element for commercially available liquid-crystal displays(LCD's)I 1,2]. However, due to the back light illumination, the operating temperature of the a-Si TFT may exceed about 70 "C. Furthermore, the long-term application of the gate bias may degrade its device performancesl3-5]. Therefore, the effects of temperature and electrical stress on the a-Si TFT performances should be investigated carefully. The purpose of this work is to report the experimental and analytical results regarding to the effects of temperature and electrical stress. Threshold voltage, field-effect mobility and source-drain current have been examined under various operating temperatures and electrical stress conditions such as stressing time and gate voltage. The trapped charge at the a-Si/silicon nitride(SiNx) interface has been characterized from the hysteresis phenomena in the transfer characteristics caused by the up-down swings of the gate voltage. Also, an analytical model employing the interface charge trapping has been implemented to clarify the degradation of a-Si TFT's and verified with the experimental results. FABRICATION OF a-Si TFT The a-Si TFT's used in this work, have the inverted staggered configuration which is the most commonly used structure for flat panel displays[6]. The chromium was deposited on the corning 7059 glass substrate by electron-beam evaporation and patterned by a standard photolithography technique for a gate electrode formation. Three layers, such as SiNx/a-Si/n~a-Si were deposited consecutively by a high vaccum plasma-enhanced CVD system ope