Effects of Various Passivation Dielectrics and Via Reservoir Lengths on Stress and Electromigration Reliability of Metal
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Effects of various passivation dielectrics and via reservoir lengths on stress and electromigration reliability of metal interconnects Young-Bae Park, Young-Ah Cho, and Won-Gyu Lee System IC R & D Center, Hynix semiconductor Inc., Cheongju, 360-480, Korea ABSTRACT Reservoir length dependencies of electromigration lifetime in multilevel interconnect were compared for two passivation dielectrics, that is, FOX (Flowable Oxide) and HDP FSG (High Density Plasma Fluorinated Silicate Glass). The higher electromigration resistance of interconnects passivated by FOX can be best explained by their lower stress and vacancy concentration levels than the case for FSG. It was also proposed that lower levels of stress and vacancy concentration in the longer reservoir could partially contribute to the better electromigration reliability of interconnect with the longer reservoir. INTRODUCTION In addition to direct stress-voiding problem, electromigration-induced voiding is also strongly influenced by the mechanical stress evolution within metal lines, especially at no current stressed region (especially, a reservoir which can be defined as an extended region of metal line under or over via) in multilevel interconnect structure [1,2]. This study reported the results of systematic experimental and computational analysis on the effects of reservoir length and passivation material on not only the distributions of both mechanical stress and vacancy concentration in reservoir region but also the electromigration reliability of multilevel
interconnect structure. Reservoir length (0.04~0.30 ) dependencies of electromigration lifetime of multilevel interconnect were compared for two passivation dielectrics, that is, FOX and FSG. EXPERIMENTAL DETAILS Electromigration test structure with two-level metallization as shown in Fig. 1 was fabricated. Plasma enhanced chemical vapor deposited (PECVD) oxide of 700nm was prepared on P-type Si wafer. A bottom-Ti (10nm)\Al-0.5%Cu (350nm)\Ti (5nm)\TiN (60nm)-top stack was then deposited using a multi-chamber dc magnetron sputtering system without vacuum break. The metal stack was then patterned by standard photolithography and plasma dry etching. Either FSG or FOX was deposited on the patterned metal lines. L6.24.1
0.75 0.04
0.425
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0.22(W), 0.75(H) 1.175
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ILD Metal
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450 Si substrate Geometry Variable: reservoir length - 0.04, 0.08, 0.12, 0.30
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Figure 1. Schematic of two-level metallization structure used in the electromigration test. This was followed by deposition of plasma enhanced tetra ethyl ortho silicate (PETEOS) film and then planarization by chemical-mechanical polishing (CMP), which results in inter-level dielectric (ILD) of either FSG\PETEOS or FOX\PETEOS. After via hole opening and Ar sputter etching were carried out, via plugs were fabricated by in-situ deposition of Ti\TiN liner, CVD W deposition, and W CMP. The same processes were repeated to make the second level structure. Reservoir length of m
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