Through-silicon via stress characteristics and reliability impact on 3D integrated circuits
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Introduction As silicon technology continues to advance following Moore’s Law, significant challenges in chip design, materials, and processes have emerged beyond the 14 nm technology node. This has led to important developments in technology, including the implementation of Cu/low-k interconnects (k is the dielectric constant), strained silicon technology, the multi-core processor, and the double gate field-effect transistor, such as the FinFET.1–5 However, the limits imposed by the wiring delay from on-chip interconnects, power dissipation, and form factor remain key concerns for technology development based on conventional two-dimensional (2D) device integration. Beyond the 14 nm node, there are basic materials and processing issues, including an increase in Cu interconnect resistivity, damage from plasma processing, and the porosity limit for the ultralow-k dielectrics. While technology developments have continued, future technologies require further optimizations in design, materials, and processing to improve device density and chip performance. Concerns of cost increase in manufacturing and degradation in yield and reliability have already
been reflected in a slower pace in recent advances of 2D integration.6 This has generated great interest from the industry to develop three-dimensional integrated circuits (3D ICs) where dies are stacked vertically to reduce the wiring delay, power dissipation, and form factor of the integrated system. While the advantages of 3D integration have been recognized for more than a decade, active developments have occurred only in the past few years. This has largely been stimulated by the mobile communication industry where device form factor, power consumption, and manufacturing costs are key drivers for technology development. In 3D integration, silicon dies are stacked vertically and through-silicon vias (TSVs) are used to provide short vertical interconnects to improve interconnect performance and system integration for 3D ICs.7–10 The TSVs are critical elements for providing not only electrical interconnects, but also thermal and mechanical functionalities to support the 3D integration. Cu is widely used to form the TSV using a process compatible with the backend integration of Cu/low-k interconnects. The fabrication of the TSV structure involves deep etching of the
Tengfei Jiang, The University of Texas at Austin, USA; [email protected] Jay Im, The University of Texas at Austin, USA; [email protected] Rui Huang, The University of Texas at Austin, USA; [email protected] Paul S. Ho, Texas Materials Institute, The University of Texas at Austin, USA; [email protected] DOI: 10.1557/mrs.2015.30
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MRS BULLETIN • VOLUME 40 • MARCH 2015 • www.mrs.org/bulletin
© 2015 Materials Research Society
THROUGH-SILICON VIA STRESS CHARACTERISTICS AND RELIABILITY IMPACT ON 3D INTEGRATED CIRCUITS
Si wafer to form via holes, depositing the barrier and seed layers, and electroplating of Cu to fill the via holes.11 Thermal stresses can arise during fabrication, testing,
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