Efficacy of Damage Annealing in Advanced Ultra-Shallow Junction Processing
- PDF / 162,789 Bytes
- 8 Pages / 612 x 792 pts (letter) Page_size
- 90 Downloads / 215 Views
1070-E04-03
Efficacy of Damage Annealing in Advanced Ultra-Shallow Junction Processing Paul Timans1, Yao Zhi Hu1, Jeff Gelpey2, Steve McCoy2, Wilfried Lerch3, Silke Paul3, Detlef Bolze4, and Hamid Kheyrandish5 1 Mattson Technology, Inc., Fremont, CA, 94538 2 Mattson Technology Canada, Inc., Vancouver, V6P 6T7, Canada 3 Mattson Thermal Products GmbH, Dornstadt, 89160, Germany 4 IHP, Frankfurt (Oder), 15236, Germany 5 CSMA Ltd., Stoke-on-Trent, ST4 7LQ, United Kingdom ABSTRACT Low thermal budget annealing approaches, such as millisecond annealing or solid-phase epitaxy (SPE) of amorphized silicon, electrically activate implanted dopants while minimizing diffusion. However, it is also important to anneal damage to the crystal lattice in order to minimize junction leakage. Annealing experiments were performed on low-energy B implants into both crystalline silicon and into wafers pre-amorphized by Ge implantation. Some wafers also received As implants for halo-style doping, and in some cases the halo implants were preannealed at 1050°C before the B-doping. The B-implants were annealed by either SPE at 650°C, spike annealing at 1050°C, or by millisecond annealing with flash-assisted RTPTM (fRTPTM) at temperatures between 1250°C and 1350°C. Residual damage was characterized by photoluminescence and non-contact junction leakage current measurements, which permit rapid assessment of damage removal efficacy. Damage from the heavy ions used for the halo and preamorphization implants dominates the defect annealing behaviour. The halo doping is the critical factor in determining junction leakage current. Spike annealing removes the damage very effectively but causes excessive dopant diffusion, whereas fRTP at temperatures >1250°C minimizes diffusion while also providing better damage annealing than is possible through SPE. INTRODUCTION Advanced CMOS devices require ultra-shallow junctions (USJ) with abrupt doping profiles and very high concentrations of electrically active dopants. USJ are usually formed by ion implantation followed by thermal annealing that electrically activates the implanted dopants and anneals damage. Minimizing residual defects in the depletion regions of p-n junctions is essential because they can greatly increase junction leakage current [1]. CMOS scaling typically increases the channel doping in order to control short-channel effects, which reduces the width of depletion regions, raising the electric field and band-to-band tunneling (BTBT) leakage. Residual defects can exacerbate the problem, for example through trap-assisted tunneling. Conventional annealing cannot electrically activate implanted dopants without simultaneously causing excessive dopant diffusion. Millisecond annealing at temperatures just below the melting point of silicon can overcome this challenge and also provide some defect annealing, but several studies have shown that conventional spike annealing is more effective in removing defects [2-5]. Another path to USJ is through low-temperature (< 650°C) SPE, where dopants are incorporat
Data Loading...
