Ultrashallow Junction Formation and Gate Activation in Deep-Submicron CMOS
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ULTRASHALLOW JUNCTION FORMATION AND GATE ACTIVATION IN DEEP-SUBMICRON CMOS P. A. Stolk, F. N. Cubaynes, V. M. H. Meyssen, G. Mannino,1 N. E. B. Cowern, J. P. van Zijl, F. Roozeboom, J. F. C. Verhoeven, J. G. M. van Berkum,2 W. M. van de Wijgert,2 J. Schmitz, H.P. Tuinhout, and P. H. Woerlee Philips Research Laboratories, Eindhoven, The Netherlands 1 INFM and Dipartimento di Fisica, Università di Catania, Catania, Italy 2 Philips Research Laboratories, CFT, Eindhoven, The Netherlands
ABSTRACT This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (~100 oC/s) and ~1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 µm device performance. The feasibility of spike annealing and poly-Si gate materials for 100-nm technology was proven by full integration using gate lengths down to 80 nm.
INTRODUCTION An essential step in the fabrication of silicon devices and integrated circuits is the controlled introduction of foreign dopant atoms in predefined areas of the silicon wafer. In the past development of devices with critical dimensions in the 10-µm range, dopants were introduced through in-diffusion from, for instance, doped silicate glass layers present on the wafer surface. In present day technology, dopants are provided through ion implantation, followed by a thermal annealing step to achieve dopant activation [1]. In this paper, we will address the role of ion implantation in the fabrication of ultrashallow junctions and the activation of polysilicon (polySi) gates in MOS transistors. The ever decreasing dimensions of MOS transistors puts increasingly higher demands on the source and drain junctions (Fig. 1): junction depths (XJ) need to be reduced while not increasing the series resistance of the device. Guidelines for the corresponding requirements on the extension and highly doped drain (HDD) junction depths and activation levels are listed in th
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