Efficient FPGA Implementation of a Digital Predistorter for Power Amplifier Linearization
- PDF / 2,475,186 Bytes
- 20 Pages / 439.37 x 666.142 pts Page_size
- 86 Downloads / 205 Views
Efficient FPGA Implementation of a Digital Predistorter for Power Amplifier Linearization Shahabuddin Rahmanian1 · Mohammad Hossein Bateni2 · Ehsan Yazdian2 Received: 12 June 2019 / Revised: 8 April 2020 / Accepted: 9 April 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents a fixed point design and implementation of a low-complexity highthroughput digital predistorter (DPD) on FPGA. Based on the memory polynomial model, a parallel structure is proposed for the implementation of the DPD and the effects of the fixed-point implementation on the performance are analyzed employing fidelity metrics such as modulation error ratio and adjacent channel power ratio. According to this analysis, an optimized fixed-point hardware implementation of the proposed DPD with proper word lengths is presented. Besides some simplifications to the proposed structure, a number of effective modifications are proposed for clock enhancement. The improved clock frequency of the proposed implementation makes it a fit choice for application over communication signals with considerable bandwidth. The required hardware and the maximum clock rate corresponding to these modifications are evaluated and reported. The performance of the proposed DPD in linearization of an actual power amplifier (PA) is also experimentally evaluated, through application of an appropriate hardware setup. Experimental results show about 11 dB ACPR improvement in the PA output for a 128-QAM test signal. The moderate hardware resource requirement of the proposed high-throughput DPD is also verified through comparison with some remarkable works in the same area. Keywords Digital pre-distorter (DPD) · Field-programmable gate array (FPGA) · Fixed-point implementation
B
Shahabuddin Rahmanian [email protected] Mohammad Hossein Bateni [email protected] Ehsan Yazdian [email protected]
1
Research institute for Avionics, Isfahan University of Technology, Isfahan 8415683111, Iran
2
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan 8415683111, Iran
Circuits, Systems, and Signal Processing
1 Introduction 1.1 Background RF power amplifiers are indispensable building blocks of almost all types of wireless communication systems. In addition to the use of M-QAM modulation with very large constellation sizes, the application of well-known techniques such as OFDM and WCDMA is widely adopted in modern wireless communication systems. Moreover, various spectrally efficient modulation techniques, such as FBMC, GFDM, UFMC, . . . , are proposed to be considered as candidates for the air interface in 5G networks [23]. High peak-to-average power ratio (PAPR) is a common feature of all these modulation schemes which necessitates the significant linearity of the employed power amplifiers (PAs). The nonlinearity of the power amplifier in general leads to distortions in both phase and amplitude of the output signal, which in turn increases the bit error rate and raises up the out of ban
Data Loading...
