Electrical Behavior of Nano-Scaled Interconnects
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Electrical Behavior of Nano-Scaled Interconnects M. Engelhardt, G. Schindler, W. Steinhögl, G. Steinlesberger, M. Traving Infineon Technologies, Corporate Research, Otto-Hahn-Ring 6, D-81730 Munich, Germany Abstract Sub-lithographic copper damascene lines were fabricated to investigate already today the physical phenomena and scaling limits of metallic conductors in the metallization systems of chip generations which are believed to be in production 10 years from now and later. Using standard manufacturing processes and state-of-the-art process tools, including standard lithography tools, narrow copper lines were fabricated at the expense of a relaxed pitch by use of a removable spacer technique. These copper nano interconnects were passivated and subjected to electrical measurements. Our results show that continuous down scaling to increase device performance will result in an unfavorable increase of the electrical resistivity of copper in stateof-the-art metallization schemes. Electrical measurements over a wide range of temperatures down to cryogenic temperatures reveal the limited potential of cooling to reduce resistivity of conductors as lateral dimensions will be shrinked down to the sub-100nm regime. By down scaling of copper diffusion barriers in damascene trenches, barrier functionality was demonstrated after high temperature anneals and excessive bias-temperature stress tests for films meeting or even exceeding end-of-roadmap thickness requirements. An analysis of the temperature dependence of the leakage current measured at very high electric fields applied between neighboring damascene lines suggests the conduction mechanism in the SiO2 used as intermetal dielectric to be Frenkel-Poole type rather than Schottky emission. Electromigration life times of sub-100nm copper lines embedded in oxide were found to be comparable with those obtained for similar structures fabricated with today’s feature sizes. Introduction A look at Table 81b in the current International Technology Roadmap for Semiconductors (ITRS, /1/) displaying the MPU interconnect long term requirements reveals that about 75% of the fields are highlighted in red, standing for “manufacturable solutions are not known”. These ITRS statements reflect that future interconnect technology is very challenging and gives rise to what people sometimes call the “interconnect crisis”. As a consequence, RC delays associated with interconnects will gain increasing importance on the overall performance of future highly integrated circuits /2/. For an early experimental assessment of the interconnect challenges ahead and of these “red brick walls”, the scaling behavior of copper damascene metallization was investigated by fabrication of hardware for an electrical characterization. Experimental Next generation lithography (NGL) required for pattern definition for the fabrication of far-inthe-future technology generations is still under investigation. Direct writing methods such as ebeam lithography are capable to define such tight feature sizes but suff
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