Processing damage and electrical performance of porous dielectrics in narrow spaced interconnects
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Processing damage and electrical performance of porous dielectrics in narrow spaced interconnects F.Iacopi1, Y.Travaly1, M.Stucchi1, H.Struyf1, S.Peeters1,2, R.Jonckheere1, L.H.A.Leunissen1, Zs.Tőkei1, V.Sutcliffe1,3, O.Richard1, M.Van Hove1 and K.Maex1,4 1
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; 2affiliate from Lam Research, Fremont, Ca.; affiliate from Texas Instruments, Dallas, Tx; 4 E.E. Dept., Katholieke Universiteit Leuven, Belgium
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ABSTRACT The damage induced in the low-k material upon exposure to dry etch and ash plasmas is a point of major concern in terms of preservation of the dielectric properties. There is urgent need to assess, classify and quantify the extent of such damage to allow the optimization of patterning processes and conditions. Meander-fork structures with spacings between 250nm and 70nm are used in this study as vehicle to compare trends in electrical performance for different dielectrics: SiO2 and two SiOC:H low-k materials with pristine k values of 3.0 and 2.6. Here we demonstrate that the ‘electrical equivalent damage’ model is a valid and precise methodology for assessing dielectric damage upon processing from interline capacitance evaluation. This analysis allows to distinguish between bulk and sidewall modification and to quantify the extent of damage. Moreover, it provides an interpretation for the degradation of leakage current and breakdown field of the interline dielectric, revealing different trends whether due to only sidewall or total damage.
INTRODUCTION The preservation of the electrical properties of low-k dielectrics throughout integration in damascene processes is an extremely challenging task. As pointed out throughout recent literature, the electrical evaluation of interconnects structures embedded in (porous) low-k dielectrics shows considerable loss in performance and reliability as compared to the use of SiO2. Moreover, the few attempts to quantify the ‘effective’ k for such structures have typically yielded values higher than those expected for low-k materials. The electrical characterization of as-deposited blanket low-k films confirms a ‘low-k’ value and shows satisfactory intrinsic dielectric properties such as leakage current and breakdown field. There is clearly a considerable amount of degradation associated to dielectric processing and integration. Such degradation can occur at various different stages of the integration processes. The electrical issues linked to an incomplete sealing of pores by a diffusion barrier layer was already addressed in several studies [1,2]. Here we focus on the dielectric modification induced by patterning processes. Previous studies have shown that porous low-k dielectrics are extremely susceptible to damage upon exposure to plasma processes, due for instance to the diffusion of reactive species into the film through the pore network [3,4]. The consequences to electrical performance become even more critical as interconnects line spacing shrinks. There is urgent need for a full understanding of such problems. Th
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