Energy efficient switching scheme based on MSB-split structure for SAR ADC
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Energy efficient switching scheme based on MSB-split structure for SAR ADC Shanshan Han1 • Lizhen Zhang1 • Jianhui Wu1,2 Received: 31 October 2019 / Revised: 26 April 2020 / Accepted: 26 July 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract An energy efficient switching algorithm for low voltage SAR ADC is presented. By the combination of MSB-split and merge-and-split techniques, this switching method consumes negative energy in the MSB bit switching, which contributes to 99.76% switching energy reduction comparing to the conventional solution. Furthermore, without requiring for a third reference voltage makes it especially suitable for ADC design under low supply voltage. Additionally, LSB-down technique is employed, which reduces the total capacitor DAC area by 50%. The simulated differential-nonlinearity and integrated-nonlinearity are 0.27 and 0.21LSB, respectively, demonstrating that the proposed switching algorithm has a relatively good linearity. Keywords Switching scheme MSB-split Merge-and-split LSB-down Low voltage SAR ADC
1 Introduction As the process size scales down, highly-digital designed SAR ADCs show convincing performance in low power consumption applications such as wireless sensor devices and biomedical devices [1]. Besides comparator and sampling switches, capacitive digital-to-analog converter (DAC) is another analog part which dominates the overall power consumption in SAR ADC. Therefore, power-efficient switching methods attract much research interest [1–10] in recent years. Comparing with conventional switching scheme [8], set-and-down [2] and Vcm -based [3] achieve 81% and 87.5% savings in switching energy, respectively. To further reduce the energy consumption, tri-level [4] and Vcm -based monotonic [5] switching procedures reduce switching energy by 96.9% and 97.7%, respectively. However, the accuracy of the third reference significantly affects the performance of ADCs. On the & Jianhui Wu [email protected] 1
National ASIC Research Center, Southeast University, Nanjing 210096, Jiangsu, China
2
Jiangsu Provincial Key Laboratory of Sensor Network Technology, Southeast University, Nanjing 210096, Jiangsu, China
other hand, the required boosted control for Vcm switching is another issue under low voltage design [6]. Recently, dual capacitor switching [9] and partial floating techniques [10] are employed, which achieve high energy-efficiency at the cost of large variation in input common-mode. In this paper, an energy efficient MSB-split switching method employing merge-and-split and LSB-down techniques is presented. The common-mode voltage keeps unchanged without the use of Vcm , which makes it especially suitable for low voltage design. Through the combination of these techniques, the proposed method achieves 99.76% saving in switching energy.
2 Proposed SAR ADC architecture The adopted architecture of the differential 10-bit SAR ADC is illustrated in Fig. 1. The capacitor array employs the MSB-splitting DAC structure simila
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