Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging
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n attractive core technology for threedimensional (3D) integration and packaging due to its various advantages such as short vertical interconnection, reduction in packaging volume, low power consumption, and multi-functionality.[1–3] TSV technologies are mainly studied for the micro-fabrication processes such as method of via formation, functional layers, via filling, wafer thinning, and stacking.[4–8] Although TSV is an advanced technology which is capable of maintaining ‘Moore’s Law’ in semiconductor integration, yet reliability and cost are still major concerns for the practical application of the product.[9–11] The major reliability problems in TSV technology include extrusion, crack, and delamination of the Cu-filled TSV which are usually caused by the mismatch of CTE between surrounding Si substrate and TSV filling metal.[12–14] Enormous amount of research activities have been performed in the past to overcome these reliability problems.[15–17] For instance, in order to suppress the Cu extrusion, Tsai et al. added the prechemical mechanical polishing (CMP) step in the middle of back end of line (BEOL) processes.[15] They carried out pre-CMP at 623 K (350 C), and succeeded in suppressing the Cu extrusion up to 50 nm at 673 K
MYONG-HOON ROH, formerly with the Department of Materials Science and Engineering, University of Seoul, Seoul 130-743, South Korea, is now Specially Appointed Researcher with the Joining and Welding Research Institute (JWRI), Osaka University, 11-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan. ASHUTOSH SHARMA, Research Professor, JUN-HYEONG LEE, Master Grade, and JAE-PIL JUNG, Professor, are with the Department of Materials Science and Engineering, University of Seoul. Contact e-mail: jpjung@ uos.ac.kr Manuscript submitted June 23, 2014. METALLURGICAL AND MATERIALS TRANSACTIONS A
(400 C). However, additional Cu-extruded region was detected in the subsequent Cu line capping layer deposition step. In other study, Ryu et al. calculated the stress distribution on the wafer, and located the devices in a position without stress called keep-away zone.[17] However, this method may cause the problem of low integration in semiconductor chips. There are various reports on the TSV filling to improve the performance and reliability, such as Cu-filled TSV with nanotwin structures.[18–21] The formation mechanism of these nanotwins is not clear which makes it difficult to control their population for large scale production.[22] Carbon nanotubes (CNTs) have also been investigated as a TSV filling material in the past. However, specialized techniques are required for CNT growth inside TSV.[23,24] Moreover, the co-plating of CNTs requires their uniform distribution inside the copper matrix which is sometimes difficult to control. In few reports, polymer filling of the TSVs has also been examined. However, there are problems of shrinkage or partial filling and polymer may degrade over time.[25,26] Recently, SiC-based and Bi-Sn-Ag solders have been tested for the TSV filling. However, extrusion properties are not discussed
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