Process development of a novel wafer level packaging with TSV applied in high-frequency range transmission
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REVIEW PAPER
Process development of a novel wafer level packaging with TSV applied in high-frequency range transmission Xiao Chen • Jiajie Tang • Gaowei Xu Le Luo
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Received: 4 September 2012 / Accepted: 6 December 2012 / Published online: 18 December 2012 Ó Springer-Verlag Berlin Heidelberg 2012
Abstract The process development of a novel wafer level packaging with TSV applied in high-frequency range transmission is presented. A specially designed TSV structure (a core TSV and six shielding TSVs) is adopted to connect the components on different sides of the highresistivity silicon wafer. And the microstrip line in the microwave monolithic integrated circuit is used to transmit high-frequency signal in packaging structure together with the low permittivity intermediate dielectric polymer, benzocyclobutene. The TSV fabrication process and the multilayer interconnection is illustrated in details. The electrical measurement result of the microstrip lines connected by TSVs reveals the resistances within 0.719 X, a return loss better than 23.8 dB and an insertion loss better than 2.60 dB from 14 to 40 GHz.
1 Introduction Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional (3D) packaging technology, in which
X. Chen (&) J. Tang G. Xu L. Luo State Key Laboratory of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China e-mail: [email protected] L. Luo e-mail: [email protected] X. Chen J. Tang Graduate School of Chinese Academy of Sciences, Beijing, China
multi-chips are assembled by vertical interconnects by through silicon vias (TSV) at wafer level packaging. 3D packaging has higher packaging density, shorter interconnection, lower noise and lower profile (Jang et al. 2007; Beica et al. 2008; Kumagai et al. 2008). In order to achieve extremely high-density integration, system-in-package (SiP) encounters the challenges in package size, process, thermal and electrical performances (Tummala and Swaminathan 2008). The 3D packaging technology with TSV may offer an optional solution to this problem. Using the TSV interconnection on SiP, the multi-layer interconnection and the active components such as MMIC chips can be separately integrated on each side of the silicon substrate. Because the MMIC chips may take the risk of the failures in the fabrication processes (Corrosion, release and high-temperature annealing) when they are integrated into the substrate. Owing to TSV, the MMIC chips can be integrated on one side of the wafer after these fabrication processes and the assembling of other devices on the other side. Not only the shortest vertical connections, less loss and parasitic effect can be ensured, but also the failure and reliability problems can be greatly decreased. Accordingly, the mass production of the substrate with integrated active/passive devices, MEMS devices and optoelectro
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