Fabrication and Characterization of 5 kV IGBTs on 4H-SiC
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0911-B10-05
Fabrication and Characterization of 5 kV IGBTs on 4H-SiC Charlotte Jonas, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, and John Palmour Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703 ABSTRACT P-channel planar IGBT devices were made on 4H-SiC. Punch-through buffer and drift layers were designed to block 5 kV were grown on 4H-SiC n-type substrate. Ion implantion was used for all selective doping such as n-well, p+, n+, JFET region and terminations. Gate oxidation was thermally grown and annealed. Blocking voltage of 5.7 kV was demonstrated. IGBTs exhibit VTH of -12 V, VT = -3.1 V, Rdiff,on = 400 mΩ·cm2 at Vg = -34 V at room temperature. Ron decreased to 108 mΩ·cm2 at Vg = -30 V at 300°C.
INTRODUCTION Power devices on SiC have clearly demonstrated their advantages over Si for high power, high temperature and high-speed applications1. The IGBT is a combination of a DMOSFET and a BJT. It combines the positive attributes of being a voltage-controlled device but has the conduction and switching characteristics of a BJT. In this paper, fabrication and characterization of p-channel IGBTs on 4H-SiC will be discussed. EPI LAYER DESIGN
4H-SiC n-type substrates. A 2 µm, p-type, 1-2 x 1017 cm-3 doped buffer layer was grown on the substrates to prevent the depletion region from punching through in the off state. A 50 µm 1-3 x 1014 p-type
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Drift layer thickness: (µm) Blocking voltage (kV)
P-channel IGBTs were fabricated on
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drift layer was grown on the buffer layer for 5 kV blocking capability. It is desirable that the drift layer be as thin as possible to reduce the on-state voltage, while maintaining the 5 kV blocking capability.
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Figure 1. Dependence of breakdown on drift layer doping and thickness in 4H- SiC.
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The selection for the doping and thickness of the drift layer was based on numerical simulations as shown in Figure 12. The maximum electric field, in this simulation, was fixed at 2 MV/cm. DEVICE FABRICATION The n-well, p+, n+, JFET region and terminations are all formed by ion implantations. The Nitrogen is implanted at 650°C with a total dose of 2.5x1014 cm-2 to form the n-well. The p+ region is implanted with a shallower dose of 3.5x1014 cm-2 of Aluminum at 650°C. The channel length is approximately 1.5 µm as defined by the spacing between the p+ and n-well. The JFET region is implanted with aluminum to prevent depletion regions of adjacent n-wells from pinching off. The spacing between adjacent n-wells is approximately 5 µm. The n+ guard ring termination is implanted at room temperature with nitrogen, while the channel stop is implanted with aluminum. Once all the implantations are complete, the wafers are annealed at 1600°C for 5 min in Argon to activate the dopants. A thin thermally grown SiO2 and thick CVD oxide are deposited over the termination region as a surface passivation. A gate oxide of 450 Å was thermally grown and
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