Fin Sidewall Microroughness Measurement by AFM
- PDF / 215,115 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 99 Downloads / 214 Views
E1.13.1
Fin Sidewall Microroughness Measurement by AFM Carolyn F. H. Gondrana, Emily Moralesa, Angela Guerrya, Weize Xiongb, C. Rinn Cleavelinc, Rick Wisec, Sriram Balasubramaniand and Tsu-Jae Kingd a International SEMATECH, Austin, TX 78741-6449 U.S.A. b X-Chips Technologies Incorporated, Austin, TX 78741-6449 U.S.A. c Texas Instruments Incorporated, Dallas TX U.S.A. d Department of Electrical Engineering and Computer Science, University of California Berkeley, Berkeley CA 94720-1770 U.S.A. ABSTRACT The sidewalls of etched Si lines will be the carrier channel surfaces in FinFET devices. These surfaces must be as smooth as possible for optimal device performance. Thus, the ability to quantitatively measure sidewall roughness is essential to process development. A methodology to quantitatively measure Fin sidewall roughness by AFM is presented. The samples were prepared for measurement by cleaving along the length of the Fins or dense-line test structures and by FIB polishing to bring the edge of the sample close to the sidewall of the etched feature. The cleaved and FIB-polished sample was mounted 17 degrees shy of normal. This exposes the sidewall on the top surface while preventing shadowing of the lower part of the sidewall due to contact between the side of the probe support and the cleaved or polished edge. Quantitative AFM measurements taken by this method show meaningful differences in the sidewall roughness for samples that have seen different sidewall smoothing treatments. The average observed rms roughness values for various surface-smoothing treatments range from 0.8 to 1.8 Å for a 50 nm square area.
INTRODUCTION As bulk-Si CMOS quickly approaches its scaling limits, new avenues are being pursued to allow continued improvement in device performance. Multiple-gate MOSFET (MuGFET) structures are very promising candidates for CMOS scaling beyond the 45nm node. They offer superior short channel effect immunity and higher drive current per unit width. MuGFET devices include the FinFET [1] triple-gate quantum-wire SOI MOSFET [2], the tri-gate MOSFET [3], the Π-gate device [4], the Ω-gate device [5], and the strained-channel multi-gate device [6]. All of these devices will have gates on raised structures, finger-like silicon “Fins.” In these structures, the channel conduction will be along the etched silicon surfaces. The as-etched surfaces are rougher and contain significantly more defects than planar epi-silicon wafer surfaces. Untreated, such defects and rough surfaces would have detrimental effects on both carrier mobility and gate oxide quality. Several process techniques have been explored to smooth the etched silicon surfaces including oxidation and hydrogen anneal [7–9]. However, because of their unique 3D geometry and small size, no systematic metrology technique has been reported to quantify the surface roughness on the sides and on the corners of the MuGFET device silicon fingers. In earlier works, atomic force microscopy (AFM) data has been taken on the sidewalls of tall lines in dense line test st
Data Loading...
