Formation of a Thermally Stable NiSi FUSI Gate Electrode by a Novel Integration Process
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0958-L06-08
Formation of a Thermally Stable NiSi FUSI Gate Electrode by a Novel Integration Process S.Y. Tan1, Hsien-Chia Chiu2, and Chun-Yen Hu2 1 Department of Electrical Engineering, Chinese Culture University, 55, Hwa-Kang Road, YangMing-Shan, Taipei, 11114, Taiwan 2 Graduate Institute of Materials Science and Nanotechnology, Chinese Culture University, 55, Hwa-Kang Road, Yang-Ming-Shan, Taipei, 11114, Taiwan
ABSTRACT Nickel silicide is promising to be the choice material as contact to the source, drain, and gate for sub-65 nm and 45 nm CMOS devices. However, the thermal stability of NiSi is worse as the high resistivity phase of NiSi2 nucleates at about 750
℃
℃ and film agglomeration occurs
even at a temperature as low as 600 . The process integration issues and formation thermally stable NiSi are needed to be understood and addressed. In order to obtain a thermally stable NiFUSI gate electrode, we introduced a novel integration process by using a two-step anneal process associating with properly tuned thickness of the initial Ni film and implant BF2 atoms during the poly-gate formation. As results, push the transformation of NiSi2 to a higher
℃.
Several measurement techniques such as XRD, TEM, SEM and temperature at about 900 Resistivity are carried out to demonstrate its physical and electrical properties. INTRODUCTION The aggressive scaling of MOSFETs is expected to lead to reduced gate dielectric thickness to below 2 nm in equivalent oxide thickness (EOT). According to the ITRS road map, in order to realize a low power CMOS of 65 nm and a 45 nm technology node by prearranged performance, it is necessary to reduce gate dielectric thickness to less than 1.5 nm in EOT and also to suppress the gate leakage current [1]. Materials with a dielectric constant higher than that of SiO2 are being subject of intensive research, since they can lead to lower leakage current while maintaining similar capacitance as compared to silicon oxide. Among them, the high-k gate dielectric can provide a relatively thicker dielectric for reduced leakage and improved gate capacitance toward sub-45nm node and beyond [2,3]. The use of poly-Si gate electrodes on high-k has brought on serious concerns. Metal gate is required for future CMOS generation to suppress boron penetration gate depletion associated with Poly-Si gate. The fully silicided gate was found to be a very simple approach [4-6]. In additional, NiSi is potentially an attractive to material due to its low resistivity, less consumption of Si, and its capability to maintain low resistivity even for line-width down to 100 nm [4,7,8]. Unfortunately, the thermal stability of NiSi is worse than TiSi2 and CoSi2 as the high resistivity phase NiSi2 nucleates at about 750
℃
℃ and film agglomeration occurs even at a temperature as
low as 600 [9]. The thermal stability of NiSi thin film and the phase transformation from NiSi to NiSi2 are important for understanding the properties of Ni-FUSI and improving the devices fabrication processes.
A fair amount of work was published
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