Heterogeneous Clustered Processors: Organisation and Design
The rapid development of electronic technology and new trends in the software market are forcing micro-architects to explore new solutions to improve performance and reliability. In this paper, we describe the idea of Heterogeneous Clustered Processors as
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Abstract. The rapid development of electronic technology and new trends in the software market are forcing micro-architects to explore new solutions to improve performance and reliability. In this paper, we describe the idea of Heterogeneous Clustered Processors as a viable alternative to well known proposals for future billion-transistor processors. The architectural model is described together with a test core and its preliminary performance evaluation.
Introduction Recent multimedia applications, portable computing and sub-micron technologies are evolving in directions that may change the shape of computing. The computer architecture community faces the challenge of how to combine standard processor design with multimedia and mobile functionality within the same package [1,2], where delays are dominated by wires and no longer by gates [3]. The possibility of integrating one billion transistors makes it possible, but an efficient architectural approach for such systems on-a-chip has to be found. In this paper, we propose a solution based on the idea of unbalanced dependence chains, called Heterogeneous Clustered Processors (HCP). This solution is a possible way to improve performance and functionality for system-on-a-chip and standard general-purpose processor. An asynchronous general-purpose processor core, called GRAVITY, is being investigating in order to evaluate design complexity and effectiveness of the proposed approach. GRAVITY has also been used to evaluate both a synchronous and an asynchronous implementation [4]; preliminary results justify preference for the latter approach. The paper is organized as follows: section 2 describes the ideas behind Heterogeneous Clustered Processors. The basic hardware properties are introduced in Section 3, some considerations about its instruction set features in Section 4. The GRAVITY core is analyzed in section 5, while preliminary performance results are analyzed in Section 6. Some conclusions are drawn in section 7.
P. Amestoy et al. (Eds.): Euro-Par’99, LNCS 1685, pp. 1296-1300, 1999. Springer-Verlag Berlin Heidelberg 1999
Heterogeneous Clustered Processors: Organisation and Design
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Heterogeneous Clustered Processors Traditional approaches to processor design share the idea of code formed by a sequence of instruction blocks, where each instruction specifies one operation and its operands. The boundaries of these blocks are represented by control instructions (e.g. branches). Instructions are arranged to allow parallel execution with dependence as constraint; all instructions share global register files. Recently, code has started to change shape [5]: instructions are replaced by one or more operations sharing a predication field. This field is used to specify a condition that must be met if the operations are to be executed. Such approaches allow breaking of the classic block boundaries, but they introduce a new global resource: the conditional register file for predication. It represents a performance bottleneck just like the register file. Some attem
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