High Conductivity Gate Metallurgy for Tft/Lcd's
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ABSTRACT Amorphous silicon based thin film transistor liquid crystal displays (TFT/LCD) have become the dominant technology used for flat panel displays for notebook computers. The need for higher resolution, larger diagonal displays for both notebook and desktop applications is discussed. Calculations have shown that the use of high conductivity gate metal such as aluminum or copper, together with the implementation of improved groundrules, can significantly extend today's technology. Aluminum suffers from problems with hillock formation during PECVD processing, and copper typically has poor adhesion to glass, reaction problems with silicon and other PECVD films, and difficulties in contacting it to other metals. Approaches to solving problems with both materials are presented, and a novel reduced mask process to fabricate high resolution, high aperture ratio 10.5" SXGA (1280x1024) displays is described. The process uses copper gate metallurgy with redundancy, without the need for extra processing steps. The resulting displays have 150 dpi color resolution, an aperture ratio of over 35%, and excellent image quality, making them the first high resolution displays that are suitable for notebook applications.
INTRODUCTION The Flat Panel Display market is growing rapidly, with the dominant technology being active matrix displays for notebooks, and increasingly for desktops. Currently used materials and processes are not always extendible as resolution and display size increase, and efforts to replace them can lead to substantial increases in manufacturing cost. Amorphous silicon technology limitations, photolithography issues (such as overlay and resolution), wet etch biases, and gate metal conductivity are among the items that must be addressed in the building of larger and higher resolution (greater than 150 dots per inch) displays'. As display size and resolution increase, the information content may fall off due to gate line delay. Factors which directly affect the gate line delay (RC) are the resistance of the metal gate line (affected by the size of the display), the capacitance associated with crossovers (where data metal crosses gate metal), the channel capacitance of the TFT, the storage capacitor, and the liquid crystal capacitance. A frame rate of 60 Hz results in a gate line time of about 16 microseconds for the TFT to charge the pixel and then turn off and hold the charge. As a result, high conductivity gate metal is required to minimize the gate delay. Figure 1 shows a plot of maximum gate resistivity vs. the number of gate lines (resolution) as a function of display diagonal. For example, the display described in
37 Mat. Res. Soc. Symp. Proc. Vol. 507 © 1998 Materials Research Society
this paper is a 10.5" diagonal SXGA display (1024 gate lines). The plot shows that the resistivity of traditionally used metallurgies such as MoW or Ta is too high to build this display.
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