High-Speed and Low-Power Performance of n-type InSb/InP and InAs/InP Core/Shell Nanowire Field Effect Transistors for CM
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High-Speed and Low-Power Performance of n-type InSb/InP and InAs/InP Core/Shell Nanowire Field Effect Transistors for CMOS Logic Applications. M. Abul Khayer, and Roger K. Lake LAboratory for Terascale and Terahertz Electronics (LATTE) Department of Electrical Engineering, University of California Riverside Riverside, CA 92521, USA, email: [email protected] ABSTRACT The performance metrics of highly scaled n-type InSb/InP and InAs/InP core/shell nanowire (NW) field-effect transistors (FETs) are theoretically investigated using an 8-band k·p model and a semiclassical ballistic transport model. We present the ON-current, the intrinsic cut-off frequency, the gate-delay time, the power-delay product, and the energy-delay product of NWFETs with two NW diameters of 10 nm and 12 nm, which operate in the quantum capacitance limit. We compare the results to the numbers predicted or projected for other materials and dimensionalities and find good agreement. Within a source Fermi energy range of 0.1 – 0.3 eV for all devices, the ON-current varies from 7 – 58 μA, the intrinsic cut-off frequency ranges from 8 – 15 THz, the power-delay product varies from 2x10-20 – 9.7x10-19 J, the gatedelay time varies from 2 – 19 fs, and the energy-delay product ranges from 7x10-35 – 1x10-32 Js. These NWFETs, thus, provide both ultra-low power switching and high-speed. INTRODUCTION InSb and InAs are being considered as attractive candidates for the channel of next generation field-effect transistors (FETs) because of their (i) high electron mobility at room temperature [1], and (ii) low contact resistance [2]. Reports by Intel and Qinetiq on the fabricated both n- and p-type InSb quantum well FETs show that InSb-based FETs can achieve equivalent high performance with lower dynamic power dissipation [3-6]. Significant performance improvement in terms of power-delay product has been reported in devices operating in the quantum capacitance limit (QCL) [7-9]. There are series of reports on the experimental realizations of InSb and InAs nanowire (NW) FETs [3-6, 10-15]. These materials have very small effective masses (0.013m0 for bulk InSb and 0.026m0 for bulk InAs, for example) which results in high electron mobility (~30,000 cm2V-1s-1 for InSb and ~20,000 cm2V-1s-1 for InAs @ ns=1x1012 cm-2) at room temperature. The low effective mass offers the high electron mobility as well as the low density-of-states. Therefore, the current drive of InSb and InAs NWFETs are questioned. Furthermore, both of these materials have a small bandgaps (0.23 eV for bulk InSb and 0.35 eV for bulk InAs, for example) which limit the voltage range of operation. In this paper, we model and theoretically investigate the performance metrics of highly scaled n-type InSb/InP and InAs/InP core/shell NWFETs using a three dimensionally discretized 8-band k∙p model [9] and a semiclassical ballistic model [16]. We present the ON-current, the intrinsic cut-off frequency, the gate-delay time, the power-delay product, and the energy-delay product of NWFETs with two NW di
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