High Temperature Plasma Etching of PZT Capacitor Stacks for High Density FERAMs
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High Temperature Plasma Etching of PZT Capacitor Stacks for High Density FERAMs Ulrich Egger, Kazuhiro Tomioka1, George Stojakovic2, Yasuyuku Taniguchi1, Rainer Bruchhaus, Haoren Zhuang, Hiroyuki Kanaya1, Gerhard Beitel, Shigeki Sugimoto1 FeRAM Development Alliance, Yokohama, JAPAN, Infineon Technologies Japan K.K. Yokohama Complex #410-1F, 8 Shinsugita-cho, Isogo-ku, Yokohama, 235-8522 Japan 1 FeRAM Development Alliance, Yokohama, JAPAN, Toshiba Corp. Semiconductor Company 2 Infineon Technologies NA Corp., East Fishkill, NY email: [email protected] ABSTRACT A 32 Mbit chain FeRAM™ stack with 0.20µm minimum feature size was etched with two subsequent lithography/RIE steps: in mask step 1 the platinum/SRO (strontium ruthenium oxide) top electrode and the PZT (lead zirconate titanate) layer, in mask step 2 the bottom electrode together with the Ir/IrO2 diffusion barrier were etched. The stack was etched with various chlorine based chemistries. High temperature etching processes were applied to suppress residues by the formation of volatile etching byproducts resulting in a highly anisotropic etching profile and low redeposition. Profile angles of 75º for step 1 and 80º for step 2 could be achieved. For the thin SRO-layer a separate etching recipe was developed to avoid surface roughening caused by micromasking. The influence of etching temperature and different gas chemistries on the etching behavior was evaluated. Reliable end point detection and good uniformity of the individual etching processes were obtained, both being crucial for the application of a multi-step recipe. The ferroelectric properties of the capacitor were confirmed by hysteresis measurements. This demonstrates that the ferroelectric properties were conserved during RIE etch processes at high temperature. INTRODUCTION Ferroelectric Random Access Memory Devices (FeRAMs) are non-volatile and combine DRAM like fast reading and writing times with low power consumption. Therefore they surpass all present mainstream memory devices in applicability. Presently, their potential is most obvious for low-power, high density mobile devices like intelligent contactless chip cards and future generations of mobile phones. Small memory cell sizes in the order of 2µm2 and below will enable production of 32Mbit and higher density FeRAMs. A chain cell design in 1T/1C operation and a capacitor on plug (COP) structure satisfy this requirement. A high taper angle is necessary for a small capacitor size due to the considerable thickness of the COP structure. The most simple approach to etch a complex capacitor stack which consists of a variety of materials would be an etch process controlled by physical sputtering. Purely sputter controlled etching processes are insensitive to different materials and bonding states [1]. Hence even a heterogeneous structure could be etched with one recipe step. However, this etching regime suffers from trenching and the formation of sidewall residues, if the sidewall taper angles are in the range above 70º. For a simpler Pt/P
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