Manufacturability Study for Etching High-Density BST/Pt Capacitors
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Manufacturability Study for Etching High-Density BST/Pt Capacitors Jay Hwang Applied Materials Inc., 974 E. Arques Ave., M/S 81330 Sunnyvale, CA 94086, U.S.A. ABSTRACT Profile control, process repeatability and productivity concerns in etching Pt electrodes are reviewed specifically for application in fabricating high-density BST/Pt capacitors. The approach of using a high temperature cathode in a high-density reactive plasma chamber has produced a repeatable >85° Pt profile, stable etch rate and low particle results over a 500-wafer marathon test. A “corrosion-like” BST defect can be prevented by adding a post etch treatment to remove any corrosive residue from the wafer surface. A feasible manufacturing solution for etching BST/Pt capacitors for future high-density DRAM application is demonstrated.
INTRODUCTION A 4x increase in DRAM storage density in every 3~4 years has been a trend for the past 20 years [1]. As a result, the DRAM design rule is shrinking, and new changes in memory cell structure and capacitor material are being proposed to accommodate for the increasing memory density [2,3]. One of the new changes in capacitor material is to use a high-? dielectric like BST (Barium Strontium Titanate) and a noble metal electrode like Pt (Platinum). BST has a dielectric constant in two orders of magnitude higher than the current silicon oxide in use. Pt electrode is chosen for its merits of low leakage current and good thermal stability compatible with BST deposition condition in a high temperature, high oxygen ambient environment. Because of the noble character of the material, Pt etching poses some technical challenges in the areas of profile control (pattern fidelity), process repeatability and productivity. This paper outlines how to overcome these challenges and to develop a manufacturing solution for etching Pt electrodes to form high-density BST/Pt capacitors.
PATTERN FIDELITY IN ETCH Many papers [4-6] have discussed the difficulty of etching Pt electrodes such as the tapering of the etched profile or a fence-like residue, see Figure 1, which may be formed on the side wall of the etched profile. These issues present a problem in transferring patterns to form high-density capacitors. The difficulty is mainly due to a re-deposition of the low volatile by-products generated from the physically dominated etching processes. This problem can be addressed by applying highly reactive gas plasma and etching the wafer at an elevated temperature [7-9]. The high-temperature etch increases the volatility of the by-products while a reactive gas plasma assists in chemical etching rather than physical sputtering, therefore avoiding the re-deposition of byproducts. Figure 2 shows a result of vertical Pt profile on 0.13 µm space obtained from a 320°C etch process in an Applied Materials DPS™ etch chamber. An oxide hard mask was used,
CC6.6.1
and the mask selectivity was about 0.5. The etched profile was >85°, and there was no fence-like residue. A schematic of DPS™ etch chamber is shown in Figure 3.
Figure 1. Fence-li
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