Homoepitaxial growth and characterization of thick SiC layers with a reduced micropipe density
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J2.1.1
Homoepitaxial growth and characterization of thick SiC layers with a reduced micropipe density H. Tsuchida, I. Kamata, S. Izumi, T. Tawara, T. Jikimoto, T. Miyanagi, T. Nakamura and K. Izumi Central Research Institute of Electric Power Industry 2-6-1 Nagasaka, Yokosuka, Kanagawa 240-0196, Japan ABSTRACT Growth technique for thick SiC epilayers with a reduced micropipe density has been developed in a vertical hot-wall CVD reactor. Micropipe closing by growing an epilayer is possible with a nearly 100% probability for 4H-SiC substrates oriented (0001) and (000-1) off-cut towards either [11-20] or [1-100]. By applying the micropipe closing technique, a high-performance Schottky barrier diode (SBD) was demonstrated on a substrate including micropipes. Growth of low-doped and thick SiC epilayers is also possible with a good morphology at a high growth rate, and 14.4 kV blocking performance was demonstrated using a 210 µm-thick epilayer. Epitaxial growth on (000-1) substrates with low doping and a low epi-induced defect density was also demonstrated. Deep centers and impurities were investigated to determine the effective lifetime killer of the epilayers. Dislocations and stacking faults in epilayers grown on 4H-SiC substrates off-cut towards different directions were also investigated.
INTRODUCTION High-voltage and low-loss silicon carbide (SiC) power devices are expected to achieve considerable improvements in performance and reduce the dimensions of power electronics equipment [1]. High-voltage Schottky barrier diodes (SBDs) with ratings of 300-1200 V and 1-20 A are now available on the market [2, 3]. High-voltage pn diodes able to withstand 19.4 kV and high-voltage switching devices able to withstand 12.5 kV have been successively obtained at the R&D level. Operation of SiC inverters with output power of more than several kW has also been achieved recently [1]. Ongoing developments in the quality of SiC materials are expected to ensure a further improvement in the performances and operating power of SiC devices. Low-doped thick epilayers are required to fabricate high-voltage SiC devices. Considerable improvements in material quality achieving low doping concentration and low trap concentration have been made [4, 5], however, defects in epilayers can still limit the performance and size of SiC devices. Micropipes and some sorts of epi-induced defects can degrade the blocking performance of SiC devices, and such defects should be reduced or eliminated to allow enlargement of the device. To obtain stable bipolar devices with a low on-state voltage, nucleation sites of extending stacking faults (SFs) caused by forward current conduction and deep levels also need to be reduced [6-8]. In this paper, we report on the development of growth techniques for low-doped thick epilayers with a reduced micropipe density in a vertical hot-wall reactor and characterization results of deep levels, dislocations and stacking faults in the epilayers.
J2.1.2
EXPERIMENT A vertical hot-wall reactor was used in this experiment [9]
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