Hot-Carrier Effect in Submicron pMOSFETs
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S. SAHA, C. S. YEH, Ph. LINDORFER, J. LUO, U. NELLORE, and B. GADEPALLY Fairchild Research Center, National Semiconductor Corporation, Santa Clara, CA 95052-8090
ABSTRACT This paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 pim devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.
INTRODUCTION It is well-known that hot-carrier effect imposes a severe limitation on MOSFET device scaling, and substrate current (Isub) is an important monitor in assessing the overall effect of hot-carriers on device performance. In general, Isub in pMOSFETs is about three to four orders of magnitude less than that of nMOSFETs because of the lower ionization rate of holes compared to electrons, and the hot-carrier induced device degradation is not as severe as in nMOSFETs. However, in deep submicron technology, the channel current in the high field region near the drain causes low-level avalanche multiplication resulting in significant Isub. Therefore, to monitor hotcarrier effect in pMOSFETs, accurate prediction of Isub is important in designing reliable advanced devices for VLSI applications. In order to suppress hot-carrier effect in advanced CMOS technology, p- Lightly Doped Drain (pLDD) structures are used to reduce the high electric field near the drain end of pMOSFETs as shown in Fig. 1. A lower p- dose is desirable to reduce the channel electric field and Isub. On the other hand, lower pLDD dose causes significant problems like "sidewall-induced pinchoff" in both source and drain p- regions, and poor device performance due to the weak gate-to-drain overlap [1]. Therefore, in designing LDD type advanced pMOSFET devices, p- dose and length must be optimized for device reliability and performance. The effect of n- LDD dose, length, and gate overlap distance on device reliability was studied in detail by Izawa et al. [1]. In this paper, the influence of pLDD parameters such as p- dose and length (Lp) on channel electric field and Isub is reported. The results were obtained by two-dimensional device simulation program MEDICI [2]. The impact ionization model for holes was calibrated and verified with the measured data for accurate simulation of Isub in submicron devices. 21 Mat. Res. Soc. Symp. Proc. Vol. 391 ©1995 Materials Research Society
Figure 1. An idealized LDD type pMOSFET structure for device simulation. Lp = pLDD len
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