SiGe pMOSFETs Fabricated on Limited Area SiGe Virtual Substrates
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SiGe pMOSFETs Fabricated on Limited Area SiGe Virtual Substrates Andrew Waite1, Urs Straube1, Neil Lloyd1, Sally Croucher1, Yue Teng Tang1, Bifeng Rong1, Alan Evans1, Tim Grasby2, Terry Whall2, Evan Parker2. 1 University of Southampton, Dept. of Electronics and Computer Science, Southampton, SO171BJ, United Kingdom. 2 University of Warwick, Dept. of Physics, Coventry, CV47AL, United Kingdom. ABSTRACT Silicon germanium pMOSFETs with channel lengths down to 0.4µm have been fabricated on limited area silicon germanium virtual substrates. The devices have a 5nm thick Si0.3Ge0.7 active layer grown by MBE on top of relaxed Si0.7Ge0.3 virtual substrate. Virtual substrates were grown on top of 10µm square silicon pillars defined by etching trenches around their perimeter into the original silicon substrate. This limits the area of the growth zone, which in turn promotes the relaxation of the virtual substrate. Electrical measurements on 2µm long channel devices show that the maximum mobility in the strained SiGe devices is 211cm2V-1cm-1, compared to 104cm2V-1cm-1 for silicon reference devices. This increase in hole mobility increases the current drive of 0.4µm devices measured at Vgt=-2V, Vds=-2.5V from 154µA/µm to 192µA/µm. INTRODUCTION There is much interest in the integration of strained material in MOSFET devices. Strained layers increase the mobility of carriers in the channels of MOSFETs and this improvement in carrier mobility in turn increases the saturation drain current drive of these devices [1-10]. In this work we report on devices with a 5nm strained Si0.3Ge0.7 active layer grown on top of a 250nm relaxed Si0.3Ge0.7 virtual substrate. A 2nm SiGe cap and a 2nm silicon cap separates the SiGe channel from the 5nm thick gate oxide. In order to allow for the mismatch between the original silicon substrate wafer and the relaxed virtual substrate, a 1µm thick graded SiGe layer was grown, graded between 0% and 30% germanium. A diagram of the layer structure is shown in figure 1. In order to promote the relaxation of the graded virtual substrate the epitaxy layers were grown on 10µm square silicon pillars, as shown in figure 2. The pillars limit the area of the growth zone, and this limited area growth technique allows misfit dislocations in the graded virtual substrate to terminate at the edges of the growth zone. This in turn reduces the amount of cross hatch on the wafer surface in the active areas [11-12]. EXPERIMENT Processing of the devices commenced with the etching of 2.5µm deep trenches into the silicon substrate wafer to define the perimeters of the 10µm square pillars. After pillar creation the wafers were implanted with phosphorus, at 2e13cm-2, 160keV and 4e12cm-2, 70keV. This dopant was activated by RTP at 1100C for 10s. The SiGe layer structure was then grown by MBE on top of the pillars. The virtual substrate consisted of a 1µm SiGe layer graded from 0% to 30%Ge and a 250nm relaxed constant composition Si0.7Ge0.3 layer grown on top of the graded layer. A 5nm strained Si0.3Ge0.7 active layer was gr
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