Role of Boron TED and Series Resistance in SiGe/Si Heterojunction pMOSFETs
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1155-C02-05
Role of Boron TED and Series Resistance in SiGe/Si Heterojunction pMOSFETs Yonghyun Kim1,2, Chang Yong Kang2, Se-Hoon Lee1,2, Prashant Majhi2, Byoung-Gi Min3, KiSeung Lee3, Donghwan Ahn1, and Sanjay K. Banerjee1 1
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas 78758, USA 2 SEMATECH Inc., 2706 Montopolis Drive, Austin, Texas 78741, USA 3 JUSUNG America Inc., 2201 Double Creek Drive Suite 5003, Round Rock, Texas, 78664, USA ABSTRACT We investigate boron transient enhanced diffusion (TED) and series resistance in SiGe/Si heterojunction channel pMOSFET. The stress gradient at the SiGe/Si interface near the gate edge in high Ge concentrations are found to determine boron TED as well as extension junction shape, which has a significant impact on the parasitic LDD and source/drain (S/D) series resistance. In addition, high Ge concentrations in the epitaxial SiGe layer on top of Si substrate result in a high sheet resistance during a 1000oC/5s rapid thermal processing (RTP), which is mainly due to alloy scattering and interface roughness scattering. INTRODUCTION Beyond the 45nm technology node, CMOS scaling has been mainly driven by highk/metal gates and stress-induced carrier mobility enhancements [1]. To overcome intrinsic limits to carrier mobility in Si, alternative materials such as SiGe and GaAs have received the consistent attentions due to their higher carrier mobility [2-4]. Process-induced channel strain engineering is also attractive, such as compressive strain with SiGe source and drain (S/D) and channel regions in Si channel pMOSFET (PMOS) for hole mobility enhancement [5-7]. Indeed, the drive current enhancement by strain engineering and the use of high mobility materials should be maximized together, while minimizing parasitic effects such as S/D extension/overlap resistance by controlling the depth and abruptness of the extension junction in MOSFETs [8, 9]. Recently, Ranade et al. demonstrated the application of SiGe in fabricating ultrashallow junction S/D extensions in bulk Si PMOS [10]. Furthermore, King et al. showed that higher B activation can be achieved in poly-SiGe with high Ge contents compared to poly-Si for a high dose (>1e15cm-2) and high energy (20keV) B implant and rapid thermal processing (RTP) [11]. Thompson et al. characterized the junction depth and sheet resistance for p+ shallow junction with B-doped low temperature molecular beam epitaxy (LTMBE) and B-implanted Si/SiGe/Si layers, showing that higher Ge mole fractions up to 40% retard B diffusion significantly [12]. However, the physical mechanisms between series resistance and boron diffusion with electrical activation in the strained SiGe/Si heterojunction layer for PMOS have not been fully studied for different SiGe layer thicknesses and Ge contents (>50%), especially with high temperature annealing. While BF2 implant is widely used for LDD formation in standard CMOS process, F effects [13-15] should be considered for reducing a juncti
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