IAM: an improved mapping on a 2-D network on chip to reduce communication cost and energy consumption
- PDF / 1,738,640 Bytes
- 15 Pages / 595.276 x 790.866 pts Page_size
- 41 Downloads / 127 Views
ORIGINAL PAPER
IAM: an improved mapping on a 2‑D network on chip to reduce communication cost and energy consumption Parisa Mazaheri Kalahroudi1 · Elham Yaghoubi1,2 · Behrang Barekatain1,2 Received: 30 August 2018 / Accepted: 24 August 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Based on the recent research, the communication cost has been the most important open issue in network on chip (NoC). In other words, the lower the communication cost, the better the performance of the NoC and the lower the energy consumption. In this regard, although different mapping algorithms are proposed, they could not efficiently address some important challenges such as high complexity, early convergence at the local optimum, and performing well for all task graphs. The proposed method named IAM (IWO algorithm mapping) is an enhanced 2D-mesh-based-NoC mapping method which adapts the invasive weed optimization (IWO) algorithm, in order to efficiently map the IP cores to routers. The obtained results indicate that the communication cost improved 13, 9, 8, 4, and 4 percent in comparison with the LMAP, the CASTNET, the CLUSTER, the NMAP, and the PSO algorithm, respectively. Regarding energy consumption, IAM outperforms the NMAP, the CASTNET, and the CMAP and the Onyx algorithms by providing 15, 10, 7, and 7 percent improvement in energy consumption, respectively. Max delay was reduced by 11, 4, 5, and 5 percent compared to NMAP, CASTNET, CMAP, and Onyx algorithms, respectively. Throughput was improved by 9, 9, 4, and 10 percent compared to NMAP, CASTNET, CMAP, and Onyx algorithms, respectively. Keywords Network on chip · Mapping · Mesh topology · Task graph · Communication cost · Energy consumption
1 Introduction Applications are becoming increasingly sophisticated, and data that need to be analyzed using computer hardware are increasing every day. Therefore, the need for computer chips that can meet today’s processing needs is obvious. So far, several technologies have been developed to enhance the processing power of computer chips. Researchers found that in order to increase the processing power of computer chips, they have to put multiple processor cores on a chip [1]. A common technology that was formerly used was system on * Elham Yaghoubi [email protected] Parisa Mazaheri Kalahroudi [email protected] Behrang Barekatain [email protected] 1
Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran
Big Data Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran
2
chip. In this technology, several processing cores were connected by a common bus. Processing cores could communicate with each other and exchange data during the execution of an application through this shared bus. However, along with its advantages, system on chip had a few problems. One of these problems was related to throughput [2]. System performance deteriorates when there is heavy processing and there is a need for sharing a l
Data Loading...
