Impact of Ge diffusion and wafer cross hatching on strained Si MOSFET electrical parameters
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Impact of Ge diffusion and wafer cross hatching on strained Si MOSFET electrical parameters Driscoll L.1, Olsen S., Chattopadhyay S.1, O’Neill A.1, Kwa K.1, Dobrosz P.2, and Bull S.2 1 School of Electrical, Electronic & Computer Engineering 2 School of Chemical Engineering & Advanced Materials University of Newcastle upon Tyne, Newcastle upon Tyne, NE1 7RU, U.K. ABSTRACT A contender for future generations of CMOS technology is the strained silicon (S-Si) MOSFET. The mobility enhancement in S-Si can be exploited to maintain the performance enhancements demanded by Moore’s law with reduced critical dimensions. S-Si is obtained by growth of a thin Si layer over a thick virtual substrate (VS) of relaxed silicon-germanium (SiGe). The mobility of a surface channel MOSFET is dependent on the quality of the silicon-oxide (Si/SiO2) interface. Ge may out diffuse from the virtual substrate to the oxide interface causing an increase in trapping density. As the Ge content in the virtual substrate increases surface roughness also increases. These phenomena both lead to a reduction in mobility. The study of a matrix of devices having variable Ge composition and S-Si thickness is crucial in deconvolving the contributions of Ge diffusion and wafer cross-hatching roughness on electrical parameters. Increasing VS Ge composition increases the Ge concentration at the SSi/SiO2 interface and cross-hatching amplitude whereas reducing S-Si channel thickness only increases Ge concentration at the S-Si/SiO2 interface and does not increase cross-hatch amplitude. Interface state density, drive current, gate leakage current, transconductance and carrier mobility data are presented for this two-dimensional space of VS composition and S-Si thickness. The relative importance of Ge diffusion and cross-hatching roughness can be seen in this data. The results of this study indicate a lower limit of 7 nm for the S-Si thickness and an upper limit of approximately 20 % Ge in the virtual substrate for the current processing technology. Understanding the performance-limiting mechanisms in S-Si is crucial in the optimisation of VS Ge composition and S-Si thickness for current and future generations of S-Si CMOS. INTRODUCTION The recent interest in the adaptation of S-Si to CMOS technology [1] requires an understanding of the impact of various performance limiting mechanisms on device characteristics in order to improve device modelling, design and circuit simulation [2]. The lattice mismatch between Si, Ge and SiGe of different alloy compositions allows S-Si layers to be formed. This results in enhanced carrier transport due to modification of the Si band structure [3]. Thick layers of SiGe grown on Si wafers become relaxed when grown sufficiently beyond their critical thickness (hc), forming the VS. This is used to proportionally apply strain to thin layers of Si grown on top of the VS by varying the Ge content. However, misfit dislocations form at the interface between Si and relaxed SiGe causing the material to have a crosshatched surface morpho
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