CMP for High Mobility Strained Si/Ge Channels
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1157-E13-02
CMP for High Mobility Strained Si/Ge Channels Kentarou Sawano1, Yasuhiro Shiraki1 and Kiyokazu Nakagawa2 1 Advanced Research Laboratories, Tokyo City University, 1-28-1 Tamazutsumi, Setagaya-ku, Tokyo 158-8557, Japan 2 Center for Crystal Science and Technology, University of Yamanashi, Miyamae-cho 7, Kofu, Yamanashi 400-8511, Japan
ABSTRACT Chemical mechanical planarization (CMP) technique has been developed for the planarization of SiGe strain relaxed buffer layers (virtual substrates). CMP successfully eliminated the surface roughness arising inevitably on the SiGe buffer layer and ultrasmooth surface with RMS roughness less than 0.5 nm was obtained. The planarized SiGe virtual substrates were applied to strained-Si and strained-Ge channel structures and significant mobility enhancements owing to the planarization were demonstrated. These results indicated that the CMP is essential technology for next generation high performance Si/Ge based devices.
INTRODUCTION Channel strain engineering has become an essential technology as a performance booster for the continued growth of future complementary metal oxide semiconductor (CMOS) since the introduction of strain into the channel can offer significant mobility enhancement owing to highly altered band structures. Among the variety of strain-inducing techniques developed, process-induced local strain has recently achieved mobility enhancement [1] and is currently the mainstream technology. In contrast, since there is 4.2% lattice mismatch between Si and Ge, Si/Ge heteroepitaxy can introduce biaxial strain into channels across a whole wafer, which is called the global strain technique. This technique has many superior advantages over the local strain technique, for example, a much larger amount of strain can be induced with much higher stability and uniformity and strain controllability is higher thanks to its independence from device processes. The globally strained channels such as strained-Si and strained-Ge are generally formed on strain relaxed SiGe buffer layers (called SiGe virtual substrates). In such structures, a quality of the SiGe virtual substrate is very crucial to obtain high carrier mobility in the strained channel since SiGe virtual substrate quality is inherited directly to the overgrown channel quality. To obtain high quality SiGe virtual substrates, various growth methods such as the compositionally graded buffer method [2,3] and the low temperature buffer method [4,5] have been developed so far. One critical problem, however, is a very large surface roughness arising on the SiGe virtual substrate. So-called crosshatch pattern appears on the surface, irrespective of growth methods. So far, much efforts have been made to reduce the roughness by means of adjusting growth parameters, but failed to realize SiGe virtual substrates with an ultra smooth surface comparable to that of a Si substrate, that is, root mean square (RMS) surface roughness of less than 1 nm. Since strain field coming from the underlying misfit dislocation arrays is re
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