Implant Dose and Spike Anneal Temperature Relationships
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Implant Dose and Spike Anneal Temperature Relationships K. K. Bourdelle, 1 A. T. Fiory,2,* H.-J. L. Gossmann,2 and S. P. McCoy3 1
Agere Systems, Orlando FL 32819 Agere Systems, Murray Hill NJ 07974 3 Vortek Industries, Vancouver, B.C., Canada V6P6T7 2
ABSTRACT The method of ion implantation and spike annealing for preparing shallow junctions suitable for the extension regions bridging the channel and source/drain contacts of CMOS transistors are studied by annealing blanket implants. Junction depths at a given sheet resistance for low energy B implants are minimized for the combination of a fast ramp with a sharp-spike anneal. This is shown to be physically based on activation energy phenomenology. The fraction of electrically activated B is insensitive to implant dose, unlike the case of transient enhanced diffusion. Arsenic implants show higher activation fraction than comparably annealed P implants, without the large transient enhanced diffusion which is attributed to P and Si-interstitial coupled diffusion. For targeted sheet resistance and junction depth, spiking temperature trends lower with implant dose, concomitant with decreasing fraction of activated dopant. INTRODUCTION Given the substantial investment of research, development and capital in ion implantation and rapid thermal annealing, the evolution of these techniques for future technology generations is of keen interest throughout the silicon integrated circuit community. At the previous symposium in this series, Gossmann et al. applied device modeling analysis to determine the components of the series resistance in the on state of MOSFETs, based on specifications in the International Technology Roadmap for Semiconductors [1]. Among potential problem areas that were identified are the contacts to the deep junctions, which may require unrealistically high dopant activation; sufficiently low sheet resistance of junction extensions, which may be already attained with current techniques; and lateral junction abruptness in the link-up region, which also correlates with off-state leakage owing to carrier spill over. It is important to recognize that specifications for future technologies continually evolve, vary with device architecture, and depend on whether designs are for high performance and speed or low power applications. Generally, however, spike annealing methods have become associated with advancements in implant and anneal strategies for junction formation [2] and also poly-Si gate electrode activation [3]. This paper presents data pointing to a physical basis for spike annealing with fast ramping rates for reducing the junction depth of B implants [4]. Additional data is presented for spike annealing of P and As implants. As annealing methods are necessarily tied to equipment capability, this issue is also investigated in the context of ramp rate and sharpness of the thermal spike. All implants used drift mode operation of production implanters. Rapid thermal annealing was done with incandescent lamp and arc lamp systems. _____
* present addres
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