Improved off-Characteristics of a-Si Vertical-Type Mosfets
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IMPROVED OFF-CHARACTERISTICS OF a-Si VERTICAL-TYPE MOSFETs,
HIROYUKI OKADA, JUN'ICHI SAKANO, SHUNRI ODA AND MASAKIYO MATSUMURA Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152, JAPAN.
ABSTRACT We propose a new structure of vertical a-Si FET with the intermediate layer between the source and drain consisting of the multi-layer structure. The mechanism of off-current in short-channel vertical-type a-Si FET is discussed. The multilayered structure is incorporated in an attempt to reduce the back gate effect. The preliminary experimental results are also presented.
INTRODUCTION Vertical transistor structure') is the most practical structure form short channel and hence high speed a-Si thin-film transistors. We have been investigating various technologies to obtain high speed a-Si TFTs. Among them three important issues are that application of highly conductive microcrystalline silicon (uc-Si) layers in the source and drain region2) so as to reduce parasitic resistances, application of self-alignment technology3) using reactive ion etching to reduce parasitic capacitances, and application of silicon-dioxide4) grown thermally inside the original a-Si layer at a temperature as low as about 250 0 C to the gate insulator in order to obtain a good a-Si/insulator interface. The device with a channel length of as short as ltm fabricated by applying simultaneously these technologies has the field-effect mobility of O.5-1cm2/Vs5, 6 ). Propagation delay time as short as 95ns has also been achieved. Since there is no difficulty in the micro-fabrication technologies in the vertical direction, the channel length can be reduced below lum and better performance will be expected,. These devices, however, are only applicable in static circuits due to their large leakage current7) under high drain voltage conditions. The possible mechanism of the leakage current in vertical a-Si TFTs is described in Fig. 1; (1) pchannel mode of operation, (2) space charge limited current,8) and (3) backgate effect, i.e., the current due to charges induced by the drain voltage. P-channel mode may be controlled by inserting the blocking contact for hole injection at the drain region or by doping slightly phosphorus in the active layer. Space charge limited current may be suppressed by employing very thin active layer. This paper deals with a method to reduce the back-gate effect by using a new device structure. Mat. Res. Soc. Symp, Proc. Vol. 118. ' 1988 Materials Research Society
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ORIGIN OF THE LARGE LEAKAGE CURRENT IN THE SHORT CHANNEL DEVICES As shown in Fig.1, some of electric flux generated from the drain of high voltage will be terminated by electrons induced electrostatically at the "back" interface between a-Si and the intermediate insulator layer. When the spacing between the source and the drain electrode is reduced, a large number of electrons are induced at the interface, resulting in the large leakage current which is no longer controllable by the gate electrode. We must thus establish the fourth novel concept for reduci
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