TCAD Modeling of Strain-Engineered MOSFETs
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0913-D05-05
TCAD Modeling of Strain-Engineered MOSFETs Lee Smith Synopsys, Inc., 700 E. Middlefield Road, M/S A14, Mountain View, CA, 94043
ABSTRACT The rapid rise of standby power in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective approach to enable significant performance improvements at similar off-state leakage. In this paper we describe how strain effects are modeled within the context of TCAD process and device simulation. We also use TCAD simulations to review some of the common approaches to engineer strain in MOSFETs and to explain how strain impacts device and circuit characteristics.
INTRODUCTION Strain engineering is rapidly becoming a ubiquitous element in modern MOSFET design [1-3]. In the current stage of technology development, much effort is being spent to model strain effects and to optimize the strain induced by various strain sources. Technology Computer Aided Design (TCAD) tools provide a convenient means of simulating the stress and strain produced during the strain-engineered process flow as well as the impact of that strain on device performance. As will be shown by example, the resulting stress and strain fields are often nonintuitive. The impact of strain on device characteristics is determined primarily through changes in the band structure. In this paper, we review how subsequent changes in carrier repopulation, effective mass, and scattering enhance, or degrade, the mobility and shift the threshold voltage for various stress configurations. In this context, optimizing the enhancement of the low-field mobility can be viewed as an exercise in band structure engineering. For high-field transport, we use Monte Carlo device simulation to investigate the impact of strain on velocity overshoot and drive current. Beyond the analysis and optimization of strain for a single device lies the next stage in strain engineering: the impact of layout. Due to the large interaction range of stress in CMOS materials, approximately 2 µm, the modeling of isolated devices is not sufficient to predict final circuit behavior. In this paper, we also review some simulation studies we have performed to investigate the impact of circuit layout on channel stress and circuit performance.
EXAMPLES OF STRAIN ENGINEERING Strain can be engineered into a conventional MOSFET structure in many different ways. These different approaches are typically categorized as either global or a local in nature. Global approaches, such as strained-Si on relaxed SiGe, attempt to induce uniform strain throughout the
Si layer across the entire wafer [4]. While this type of approach has received a great deal of academic interest, the first approaches used in production have been of the local type [1]. Local, or process-induced, strain engineering focuses on producing stress in the channel of a single device. Figure 1 shows two of the most commonly used local approac
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