Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs
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Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs Christopher W. Leitz, Matthew T. Currie, Minjoo L. Lee, Zhi-Yuan Cheng, Dimitri. A. Antoniadis1, Eugene A. Fitzgerald Department of Materials Science and Engineering, Massachusetts Institute of Technology Cambridge, MA 02139 1 Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology Cambridge, MA 02139 ABSTRACT Strained Si- and SiGe-based heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation complementary MOSFET (CMOS) devices. The most heavily investigated heterostructures consist of single strained Si layers grown upon relaxed SiGe substrates. While this configuration offers significant performance gains for both n- and p-MOSFETs, the enhanced hole mobility remains much lower than the enhanced electron mobility. By contrast, a combination of buried compressively strained Si1-yGey layers and tensile strained Si surface layers grown on relaxed Si1-xGex (x < y), hereafter referred to as dual channel heterostructures, offers nearly symmetric electron and hole mobilities without compromising n-MOSFET device performance. To investigate these heterostructures, we study the effects of alloy scattering on channel mobility in long channel MOSFETs. By using the combination of a buried Si0.2Ge0.8 channel and a strained Si surface channel grown on a relaxed Si0.5Ge0.5 virtual substrate, we have achieved nearly symmetric electron and hole mobility in the same heterostructure. By employing different virtual substrate compositions, we can decouple the effects of strain and alloy scattering in both tensile strained surface channels and compressively strained buried channels. We show that significant hole mobility enhancements can be achieved in dual channel heterostructures, even for buried channel compositions where alloy scattering is expected to be most severe. Furthermore, we show that alloy scattering in tensile strained SiGe surface channels impacts electrons much more severely than holes. Taken together, these results demonstrate that dual channel heterostructures can offer symmetric carrier mobilities and provide excellent performance gains for CMOS applications. INTRODUCTION The rapid increase in silicon-based CMOS speed and functionality and concomitant drop in cost per device over the past several decades has been the result of aggressive scaling of MOSFET device dimensions. However, we are fast approaching a convergence of various physical and economic factors that will halt device scaling, putting an end to the incredible pace of CMOS performance advancements. A promising means of improving performance and functionality of Si-based CMOS is through the use of relaxed, low defect density silicongermanium virtual substrates1,2 as an integration platform for high mobility MOSFETs. The most heavily investigated and easily i
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