Effects of Poly-Si Annealing on Gate Oxide Charging Damage in Poly-Si Gate Etching Process
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Effects of Poly-Si Annealing on Gate Oxide Charging Damage in Poly-Si Gate Etching Process Daniel Chong, Won Jong Yoo, Lap Chan1, and Alex See1 National University of Singapore, Dept of Electrical and Computer Engineering, Silicon Nano Device Laboratory, 10 Kent Ridge Crescent, Singapore 119260 1 Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, Street 2, Singapore 738406 ABSTRACT The effects of the poly-Si annealing on gate oxide charging damage in the gate etching process were investigated. Our electrical test results show that gate oxide charging damage can be reduced if the poly-Si is not annealed prior to the gate etching process.
INTRODUCTION Poly-Si annealing is performed prior to poly-Si gate etching in certain process flows to activate the implanted dopants inside the poly-Si gates. This step forms the first part of a two-step annealing/activation process for the poly-Si gates. The second part of this two-step annealing process is performed during the source and drain junctions annealing. The reason for having a two-step polySi gate electrode annealing process is that the thermal budget required to activate the source and drain junction dopants can be kept relatively low without affecting the resistivity of the gate electrodes. Thermal budget for source and drain junction annealing/activation is kept low to obtain shallow junction devices. In this study, we wish to demonstrate the effects of the two-step poly-Si gate electrode annealing process on gate oxide charging damage.
EXPERIMENTAL DETAILS The wafers used in this study are processed up to the first metal interconnects layer using the 0.15µm technology process flow. Transistors in the test structures are n-channel devices with gate oxide thickness of 65Å. The dimension of the gate oxide is 0.15µm x 10µm. The thickness of poly-Si is 2000Å and the implanted phosphorus dose is 5.5x1015 cm-2. To investigate the effect of poly-Si annealing on gate oxide charging damage, an experimental split is performed at this step. One set of wafers undergo this step while another set skips it. Except for this step, the two sets of wafers are processed together. Poly-Si annealing is carried out in N2 ambient at 800oC for 15 minutes. Poly-Si gates are then etched in subsequent process step using an ICP etcher. The RF power and pressure at the main etch step are 200W and 5mT, whereas at the overetch step, they are 200W and 80mT. The etching gases used are HBr and HeO2. Table 1 shows a simplified process flow highlighting the first and second parts of the poly-Si annealing. Edge-intensive poly-Si antennas are used for monitoring gate oxide charging damage during poly-Si gate etching. The antenna ratios used range from 300 to 120k. They are obtained by dividing a perimeter of an antenna by a gate oxide area. In our study, the extent of plasma charging damage B4.16.1 Downloaded from https://www.cambridge.org/core. UNSW Library, on 19 Sep 2017 at 11:32:54, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms.
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