Integration Challenges for Double-Gate MOSFET Technologies
- PDF / 159,527 Bytes
- 10 Pages / 612 x 792 pts (letter) Page_size
- 41 Downloads / 216 Views
Integration challenges for double-gate MOSFET technologies W.P.Maszara Strategic Technology Group, Advanced Micro Devices Sunnyvale, CA 94088-3453 ABSTRACT Device modeling data and some early experiments suggests that fully depleted MOSFET devices where channel is controlled by two opposing gates or one gate that surrounds most or the entire channel, will provide better scaling than the classic devices with one gate on one side of the channel. However, formation of such devices requires complex, non-conventional and sometimes exotic geometry and processing, ranging from wafer bonding to selective lateral ‘tunnel’ epitaxy, to selectively wet-etched channels with triangular cross-section. Classic singlegate transistors have been recently demonstrated with reasonable performance at 20-15 nm of physical gate length. Double-gate transistors with their process integration complexity will likely become a viable alternative for smaller geometries. This paper will discuss various approaches to realization of those multi-gate fully depleted devices and their process integration challenges for sub-15 nm gates. INTRODUCTION
Node, Gate length [nm]
Collective wisdom of semiconductor technologists of the world about the future of CMOS technology expressed in annually updated International Technology Roadmap for Semiconductors (ITRS) [1] leaves an optimistic though challenging notion that the scaling of transistors will continue into a foreseeable future. A more or less constant rate of about 30% decrease of transistor size every 2 years, observed for many past technology generations and commonly known as Moore’s Law is forecasted to slow down to about 30% shrinkage every three years past the 100nm technology node, corresponding to physical gate length (Lgate) of about 45nm (Fig. 1). While new materials for gate dielectric and gate Technology Nodes and Transistor Gate electrode are widely expected to come Lengths Roadmap for Microprocessors along and help make the forecast true, it 1000 is not clear if the classic single-gate (SG) Technol. node transistor MOSFET architecture will MPU Lgate 100 need to be replaced by a different one for the next 15 years – the horizon of ITRS forecast. Recent publications show that 10 single-gate transistors with Lgate =35nm high k dielectric quickly approach the level of & metal gate performance set by ITRS [2, 3, 4] and 1 exploratory work of 20-15nm devices [5, 1995 2000 2005 2010 2015 2020 6, 7] shows very promising results. The Year classic approach to MOSFETs has been in production for well over 30 years. The inertia of this design – relative simplicity Figure 1. Technology roadmap for high performance logic transistor nodes and gate lengths [data from Ref.1]. of processing, well-understood A2.5.1
integration challenges, circuit design issues and production tools - will likely carry the single gate through the 45 nm technology node (Lgate =18nm). DOUBLE GATE ADVANTAGE Double gate (DG) MOSFETs are believed a promising alternative beyond that stage, for Lgate ≤ 13 nm (32 nm technology node).
Data Loading...
