3D System Integration Technologies
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3D System Integration Technologies Peter Ramm, Armin Klumpp, Reinhard Merkel, Josef Weber, Robert Wieland, Andreas Ostmann 1, Jürgen Wolf 1 Fraunhofer Institute for Reliability and Microintegration, Munich Division Hansastrasse 27d, 80686 Munich, Germany [email protected] 1 Technical University of Berlin Gustav-Meyer-Allee 25, 13355 Berlin, Germany ABSTRACT In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multifunctionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called "wiring crisis"), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance. The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration. INTRODUCTION Several companies and research institutes all over the world are currently working on the development of 3D system integration technologies. Industrial users are for example working in the areas of high-density memories, high performance processors, real time image processing and aerospace applications. Besides approaches based on fabrication of multiple device layers using recrystallization or epitaxial growth of Si [2], the large spectrum of technological concepts can be classified in three categories: a) Stacking of packages, b) Stacking of chips and c) Vertical system integration by wafer stacking or chip-to-wafer stacking, respectively.
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