Ion implantation for low-resistive source/drain contacts in FinFET devices
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1070-E02-01
Ion implantation for low-resistive source/drain contacts in FinFET devices Mark J. H. van Dal1, Ray Duffy1, Bartek J. Pawlak1, Nadine Collaert2, Malgorzata Jurczak2, and Robert J. P. Lander1 1 NXP-TSMC Research Center, Kapeldreef 75, Leuven, 3001, Belgium 2 IMEC, Kapeldreef 75, Leuven, 3001, Belgium ABSTRACT FinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation. INTRODUCTION Multi-gate metal-oxide-semiconductor (MOS) devices and in particular Fin Field Effect Transistors (FinFETs) exhibit excellent SCE immunity due to the superior electrostatic gate coupling to the channel [1-5], enabling the aggressive scaling of CMOS technologies beyond the 32nm node. Furthermore because of the fully-depleted nature of the device no channel doping is needed to adjust the threshold voltages of the device. This eliminates dopant fluctuations, which dramatically improves variability compared to bulk CMOS. Figure 1 shows a schematic of a FinFET device. A FinFET consists of a vertical standing Si body (fin) and the gate is wrapped around either side creating two channels on the sides and one on the top. An important advantage of the FinFET compared to alternative planar double gate architectures is that gates are self-aligned and can be fabricated with a single lithography and etch step. High-aspect-ratio trigate FinFETs with aggressively scaled fin widths (20 nm and narrower) are of particular interest as they combine excellent SCE immunity with high drivability per unit chip area.
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Figure 1. Schematic drawing of a Silicon-on-Insulator (SOI) FinFET with three fins in parallel. As the device width of a FinFET is defined as the sum of the side and the top surface dimensions, optimization of the side surface (sidewall) doping for extension and Highly Doped Drains (HDDs) can add an extra degree of freedom for improved FinFET performance. However, the 3D configuration also imposes a challenge to form low-resistive contacts, especially for the extensions. A conformal deposition and in-diffusion methodo
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